Change in coreboot[master]: mb/asus/p2b/dsdt.asl: Align POST code ASL stuff

[Angel Pons (Code Review)]

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63987 )

Change subject: mb/asus/p2b/dsdt.asl: Align POST code ASL stuff
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mb/asus/p2b/dsdt.asl: Align POST code ASL stuff

Align POST code ASL elements with existing code in newer southbridges.
The main differences are that `NoLock` is changed to `Lock`, and that
names have been changed. The lock type change should not be a problem
because the field is only used once in the _PTS method.

Change-Id: I8aa362007ff98e5b42add6c7908a8f7beac2222b
Signed-off-by: Angel Pons 
---
M src/mainboard/asus/p2b/dsdt.asl
1 file changed, 6 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/63987/1

diff --git a/src/mainboard/asus/p2b/dsdt.asl b/src/mainboard/asus/p2b/dsdt.asl
index 2c88cf6..25515d2 100644
--- a/src/mainboard/asus/p2b/dsdt.asl
+++ b/src/mainboard/asus/p2b/dsdt.asl
@@ -22,10 +22,12 @@
    #include <acpi/dsdt_top.asl>
    /* _SB scope defining the main processor is generated in SSDT. */

-	OperationRegion(X80, SystemIO, 0x80, 1)
-	Field(X80, ByteAcc, NoLock, Preserve)
+	/* Port 80 POST */
+
+	OperationRegion (POST, SystemIO, 0x80, 1)
+	Field (POST, ByteAcc, Lock, Preserve)
    {
-		P80, 8
+		DBG0, 8
    }

/*
@@ -77,7 +79,7 @@
    	/* Arms SMI for device 12 */
    	TO12 = 1
    	/* Put out a POST code */
-		P80 = Arg0 | 0xF0
+		DBG0 = Arg0 | 0xF0
    }

Method (_WAK, 1, NotSerialized)