Change in ...coreboot[master]: mb/google/sarien: Create VR config settings

[Roy Mingi Park (Code Review)]

Roy Mingi Park has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31380

Change subject: mb/google/sarien: Create VR config settings
......................................................................

mb/google/sarien: Create VR config settings

Create VR settings configuration as per board design.

BUG=N/A
TEST=Build and boot up into sarien platform.

Change-Id: Ifa1f704369ef9d2fc0a31f370f162250402605f2
Signed-off-by: Roy Mingi Park 
---
M src/mainboard/google/sarien/variants/arcada/devicetree.cb
M src/mainboard/google/sarien/variants/sarien/devicetree.cb
2 files changed, 152 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/31380/1

diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
index a47a53d..3a50480 100644
--- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
@@ -42,6 +42,82 @@
    register "SlowSlewRateForSa" = "0"
    register "SlowSlewRateForFivr" = "0"

+    # VR Settings Configuration for 4 Domains
+    #+----------------+-------+-------+-------+-------+
+    #| Domain/Setting |  SA   |  IA   | GTUS  |  GTS  |
+    #+----------------+-------+-------+-------+-------+
+    #| Psi1Threshold  | 20A   | 20A   | 20A   | 20A   |
+    #| Psi2Threshold  | 5A    | 5A    | 5A    | 5A    |
+    #| Psi3Threshold  | 1A    | 1A    | 1A    | 1A    |
+    #| Psi3Enable     | 1     | 1     | 1     | 1     |
+    #| Psi4Enable     | 1     | 1     | 1     | 1     |
+    #| ImonSlope      | 0     | 0     | 0     | 0     |
+    #| ImonOffset     | 0     | 0     | 0     | 0     |
+    #| IccMax         | 6A    | 70A   | 31A   | 31A   |
+    #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
+    #| AcLoadline     | 10.3  | 1.8   | 3.1   | 3.1   |
+    #| DcLoadline     | 10.3  | 1.8   | 3.1   | 3.1   |
+    #+----------------+-------+-------+-------+-------+
+    register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
+        .vr_config_enable = 1,
+        .psi1threshold = VR_CFG_AMP(20),
+        .psi2threshold = VR_CFG_AMP(5),
+        .psi3threshold = VR_CFG_AMP(1),
+        .psi3enable = 1,
+        .psi4enable = 1,
+        .imon_slope = 0x0,
+        .imon_offset = 0x0,
+        .icc_max = VR_CFG_AMP(6),
+        .voltage_limit = 1520,
+        .ac_loadline = 1030,
+        .dc_loadline = 1030,
+    }"
+
+    register "domain_vr_config[VR_IA_CORE]" = "{
+        .vr_config_enable = 1,
+        .psi1threshold = VR_CFG_AMP(20),
+        .psi2threshold = VR_CFG_AMP(5),
+        .psi3threshold = VR_CFG_AMP(1),
+        .psi3enable = 1,
+        .psi4enable = 1,
+        .imon_slope = 0x0,
+        .imon_offset = 0x0,
+        .icc_max = VR_CFG_AMP(70),
+        .voltage_limit = 1520,
+        .ac_loadline = 180,
+        .dc_loadline = 180,
+    }"
+
+    register "domain_vr_config[VR_GT_UNSLICED]" = "{
+        .vr_config_enable = 1,
+        .psi1threshold = VR_CFG_AMP(20),
+        .psi2threshold = VR_CFG_AMP(5),
+        .psi3threshold = VR_CFG_AMP(1),
+        .psi3enable = 1,
+        .psi4enable = 1,
+        .imon_slope = 0x0,
+        .imon_offset = 0x0,
+        .icc_max = VR_CFG_AMP(31),
+        .voltage_limit = 1520,
+        .ac_loadline = 310,
+        .dc_loadline = 310,
+    }"
+
+    register "domain_vr_config[VR_GT_SLICED]" = "{
+        .vr_config_enable = 1,
+        .psi1threshold = VR_CFG_AMP(20),
+        .psi2threshold = VR_CFG_AMP(5),
+        .psi3threshold = VR_CFG_AMP(1),
+        .psi3enable = 1,
+        .psi4enable = 1,
+        .imon_slope = 0x0,
+        .imon_offset = 0x0,
+        .icc_max = VR_CFG_AMP(31),
+        .voltage_limit = 1520,
+        .ac_loadline = 310,
+        .dc_loadline = 310,
+    }"
+
    # Intel Common SoC Config
    register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)"	# Left Type-C Port
    register "usb2_ports[1]" = "USB2_PORT_LONG(OC0)"	# Left Type-A Port
diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
index d3d26f9..bb94209 100644
--- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
@@ -46,6 +46,82 @@
    register "tdp_pl2_override" = "51"
    register "Device4Enable" = "1"

+    # VR Settings Configuration for 4 Domains
+    #+----------------+-------+-------+-------+-------+
+    #| Domain/Setting |  SA   |  IA   | GTUS  |  GTS  |
+    #+----------------+-------+-------+-------+-------+
+    #| Psi1Threshold  | 20A   | 20A   | 20A   | 20A   |
+    #| Psi2Threshold  | 5A    | 5A    | 5A    | 5A    |
+    #| Psi3Threshold  | 1A    | 1A    | 1A    | 1A    |
+    #| Psi3Enable     | 1     | 1     | 1     | 1     |
+    #| Psi4Enable     | 1     | 1     | 1     | 1     |
+    #| ImonSlope      | 0     | 0     | 0     | 0     |
+    #| ImonOffset     | 0     | 0     | 0     | 0     |
+    #| IccMax         | 6A    | 70A   | 31A   | 31A   |
+    #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
+    #| AcLoadline     | 10.3  | 1.8   | 3.1   | 3.1   |
+    #| DcLoadline     | 10.3  | 1.8   | 3.1   | 3.1   |
+    #+----------------+-------+-------+-------+-------+
+    register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
+        .vr_config_enable = 1,
+        .psi1threshold = VR_CFG_AMP(20),
+        .psi2threshold = VR_CFG_AMP(5),
+        .psi3threshold = VR_CFG_AMP(1),
+        .psi3enable = 1,
+        .psi4enable = 1,
+        .imon_slope = 0x0,
+        .imon_offset = 0x0,
+        .icc_max = VR_CFG_AMP(6),
+        .voltage_limit = 1520,
+        .ac_loadline = 1030,
+        .dc_loadline = 1030,
+    }"
+
+    register "domain_vr_config[VR_IA_CORE]" = "{
+        .vr_config_enable = 1,
+        .psi1threshold = VR_CFG_AMP(20),
+        .psi2threshold = VR_CFG_AMP(5),
+        .psi3threshold = VR_CFG_AMP(1),
+        .psi3enable = 1,
+        .psi4enable = 1,
+        .imon_slope = 0x0,
+        .imon_offset = 0x0,
+        .icc_max = VR_CFG_AMP(70),
+        .voltage_limit = 1520,
+        .ac_loadline = 180,
+        .dc_loadline = 180,
+    }"
+
+    register "domain_vr_config[VR_GT_UNSLICED]" = "{
+        .vr_config_enable = 1,
+        .psi1threshold = VR_CFG_AMP(20),
+        .psi2threshold = VR_CFG_AMP(5),
+        .psi3threshold = VR_CFG_AMP(1),
+        .psi3enable = 1,
+        .psi4enable = 1,
+        .imon_slope = 0x0,
+        .imon_offset = 0x0,
+        .icc_max = VR_CFG_AMP(31),
+        .voltage_limit = 1520,
+        .ac_loadline = 310,
+        .dc_loadline = 310,
+    }"
+
+    register "domain_vr_config[VR_GT_SLICED]" = "{
+        .vr_config_enable = 1,
+        .psi1threshold = VR_CFG_AMP(20),
+        .psi2threshold = VR_CFG_AMP(5),
+        .psi3threshold = VR_CFG_AMP(1),
+        .psi3enable = 1,
+        .psi4enable = 1,
+        .imon_slope = 0x0,
+        .imon_offset = 0x0,
+        .icc_max = VR_CFG_AMP(31),
+        .voltage_limit = 1520,
+        .ac_loadline = 310,
+        .dc_loadline = 310,
+    }"
+
    # Intel Common SoC Config
    register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)"	# Left Type-C Port
    register "usb2_ports[1]" = "USB2_PORT_LONG(OC0)"	# Right Type-A Port 1

[Roy Mingi Park (Code Review)]

Hello build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/31380

to look at the new patch set (#2).

Change subject: mb/google/sarien: Create VR config settings
......................................................................

mb/google/sarien: Create VR config settings

Create VR settings configuration as per board design.

BUG=N/A
TEST=Build and boot up into sarien platform.

Change-Id: Ifa1f704369ef9d2fc0a31f370f162250402605f2
Signed-off-by: Roy Mingi Park 
---
M src/mainboard/google/sarien/variants/arcada/devicetree.cb
M src/mainboard/google/sarien/variants/sarien/devicetree.cb
2 files changed, 152 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/31380/2

[Roy Mingi Park (Code Review)]

Roy Mingi Park has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31380 )

Change subject: mb/google/sarien: Create VR config settings
......................................................................

Patch Set 2:

This change is ready for review.

[Roy Mingi Park (Code Review)]

Roy Mingi Park has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/31380 )

Change subject: mb/google/sarien: Create VR config settings
......................................................................

Abandoned

will resubmit

[Roy Mingi Park (Code Review)]

Roy Mingi Park has restored this change. ( https://review.coreboot.org/c/coreboot/+/31380 )

Change subject: mb/google/sarien: Create VR config settings
......................................................................

Restored

[Roy Mingi Park (Code Review)]

Roy Mingi Park has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/31380 )

Change subject: mb/google/sarien: Create VR config settings
......................................................................

Abandoned