Change in ...coreboot[master]: soc/intel/apl: Configure LPC serial IRQ mode

[Nico Huber (Code Review)]

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29901

Change subject: soc/intel/apl: Configure LPC serial IRQ mode
......................................................................

soc/intel/apl: Configure LPC serial IRQ mode

Sync the FSP settings with what coreboot does. Why both FSP and coreboot
configure this redundantly stays a secret.

TEST=Set SERIRQ_CONTINUOUS on kontron/mal10. A CPLD connected to LPC
     works correctly now, but was confused by the wrong settings before
     because the FSP defaults allowed to disable the LPC clock.

Change-Id: Id1c7180f460678bf0f9458228591050dd628c052
Signed-off-by: Nico Huber 
---
M src/soc/intel/apollolake/chip.c
1 file changed, 15 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/29901/1

diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index cbd5aba..77b82d4 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -610,6 +610,21 @@
    memcpy(silconfig->PcieRpHotPlug, cfg->pcie_rp_hotplug_enable,
           sizeof(silconfig->PcieRpHotPlug));

+	switch (cfg->serirq_mode) {
+	case SERIRQ_QUIET:
+		silconfig->SirqEnable = 1;
+		silconfig->SirqMode = 0;
+		break;
+	case SERIRQ_CONTINUOUS:
+		silconfig->SirqEnable = 1;
+		silconfig->SirqMode = 1;
+		break;
+	case SERIRQ_OFF:
+	default:
+		silconfig->SirqEnable = 0;
+		break;
+	}
+
    if (cfg->emmc_tx_cmd_cntl != 0)
    	silconfig->EmmcTxCmdCntl = cfg->emmc_tx_cmd_cntl;
    if (cfg->emmc_tx_data_cntl1 != 0)