Change in coreboot[master]: intel/baytrail: Reorganize romstage.c

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34910 )

Change subject: intel/baytrail: Reorganize romstage.c
......................................................................

intel/baytrail: Reorganize romstage.c

Done just for future review convenience.

Change-Id: I9cfb0a8177c8ca18947ef0109550a36aa4333383
Signed-off-by: Kyösti Mälkki 
---
M src/soc/intel/baytrail/romstage/romstage.c
1 file changed, 74 insertions(+), 74 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/34910/1

diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index d3ea84e..834a8bc 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -40,33 +40,6 @@
 #include <soc/romstage.h>
 #include <soc/spi.h>

-/* The cache-as-ram assembly file calls romstage_main() after setting up
- * cache-as-ram.  romstage_main() will then call the mainboards's
- * mainboard_romstage_entry() function. That function then calls
- * romstage_common() below. The reason for the back and forth is to provide
- * common entry point from cache-as-ram while still allowing for code sharing.
- * Because we can't use global variables the stack is used for allocations --
- * thus the need to call back and forth. */
-
-static struct postcar_frame early_mtrrs;
-
-static void fill_postcar_frame(struct postcar_frame *pcf);
-
-/* prepare_and_run_postcar() determines the stack to use after
- * cache-as-ram is torn down as well as the MTRR settings to use. */
-static void prepare_and_run_postcar(struct postcar_frame *pcf)
-{
-	if (postcar_frame_init(pcf, 0))
-		die("Unable to initialize postcar frame.\n");
-
-	fill_postcar_frame(pcf);
-
-	postcar_frame_common_mtrrs(pcf);
-
-	run_postcar_phase(pcf);
-	/* We do not return here. */
-}
-
 static void program_base_addresses(void)
 {
    uint32_t reg;
@@ -112,53 +85,6 @@
    write32(bcr, reg);
 }

-/* Entry from cache-as-ram.inc. */
-static void romstage_main(uint64_t tsc)
-{
-	struct romstage_params rp = {
-		.mrc_params = NULL,
-	};
-
-	/* Save initial timestamp from bootblock. */
-	timestamp_init(tsc);
-
-	/* Save romstage begin */
-	timestamp_add_now(TS_START_ROMSTAGE);
-
-	program_base_addresses();
-
-	tco_disable();
-
-	byt_config_com1_and_enable();
-
-	console_init();
-
-	spi_init();
-
-	set_max_freq();
-
-	punit_init();
-
-	gfx_init();
-
-	/* Call into mainboard. */
-	mainboard_romstage_entry_rp(&rp);
-
-	if (CONFIG(SMM_TSEG))
-		smm_list_regions();
-
-	prepare_and_run_postcar(&early_mtrrs);
-	/* We do not return here. */
-}
-
-/* This wrapper enables easy transition towards C_ENVIRONMENT_BOOTBLOCK,
- * keeping changes in cache_as_ram.S easy to manage.
- */
-asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist)
-{
-	romstage_main(base_timestamp);
-}
-
 static struct chipset_power_state power_state;

static void migrate_power_state(int is_recovery)
@@ -228,6 +154,72 @@
    return prev_sleep_state;
 }

+/* The cache-as-ram assembly file calls romstage_main() after setting up
+ * cache-as-ram.  romstage_main() will then call the mainboards's
+ * mainboard_romstage_entry() function. That function then calls
+ * romstage_common() below. The reason for the back and forth is to provide
+ * common entry point from cache-as-ram while still allowing for code sharing.
+ * Because we can't use global variables the stack is used for allocations --
+ * thus the need to call back and forth. */
+
+static struct postcar_frame early_mtrrs;
+
+static void fill_postcar_frame(struct postcar_frame *pcf);
+
+/* prepare_and_run_postcar() determines the stack to use after
+ * cache-as-ram is torn down as well as the MTRR settings to use. */
+static void prepare_and_run_postcar(struct postcar_frame *pcf)
+{
+	if (postcar_frame_init(pcf, 0))
+		die("Unable to initialize postcar frame.\n");
+
+	fill_postcar_frame(pcf);
+
+	postcar_frame_common_mtrrs(pcf);
+
+	run_postcar_phase(pcf);
+	/* We do not return here. */
+}
+
+/* Entry from cache-as-ram.inc. */
+static void romstage_main(uint64_t tsc)
+{
+	struct romstage_params rp = {
+		.mrc_params = NULL,
+	};
+
+	/* Save initial timestamp from bootblock. */
+	timestamp_init(tsc);
+
+	/* Save romstage begin */
+	timestamp_add_now(TS_START_ROMSTAGE);
+
+	program_base_addresses();
+
+	tco_disable();
+
+	byt_config_com1_and_enable();
+
+	console_init();
+
+	spi_init();
+
+	set_max_freq();
+
+	punit_init();
+
+	gfx_init();
+
+	/* Call into mainboard. */
+	mainboard_romstage_entry_rp(&rp);
+
+	if (CONFIG(SMM_TSEG))
+		smm_list_regions();
+
+	prepare_and_run_postcar(&early_mtrrs);
+	/* We do not return here. */
+}
+
 /* Entry from the mainboard. */
 void romstage_common(struct romstage_params *params)
 {
@@ -255,6 +247,14 @@
    romstage_handoff_init(prev_sleep_state == ACPI_S3);
 }

+/* This wrapper enables easy transition towards C_ENVIRONMENT_BOOTBLOCK,
+ * keeping changes in cache_as_ram.S easy to manage.
+ */
+asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist)
+{
+	romstage_main(base_timestamp);
+}
+
 static void fill_postcar_frame(struct postcar_frame *pcf)
 {
    uintptr_t top_of_ram;

[Kyösti Mälkki (Code Review)]

Hello Patrick Rudolph, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/34910

to look at the new patch set (#2).

Change subject: intel/baytrail: Reorganize romstage.c
......................................................................

intel/baytrail: Reorganize romstage.c

Done just for future review convenience.

Change-Id: I9cfb0a8177c8ca18947ef0109550a36aa4333383
Signed-off-by: Kyösti Mälkki 
---
M src/soc/intel/baytrail/romstage/romstage.c
1 file changed, 75 insertions(+), 75 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/34910/2

[Kyösti Mälkki (Code Review)]

Hello Patrick Rudolph, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/34910

to look at the new patch set (#4).

Change subject: intel/baytrail: Reorganize romstage.c
......................................................................

intel/baytrail: Reorganize romstage.c

Done just for future review convenience.

Change-Id: I9cfb0a8177c8ca18947ef0109550a36aa4333383
Signed-off-by: Kyösti Mälkki 
---
M src/soc/intel/baytrail/romstage/romstage.c
1 file changed, 58 insertions(+), 58 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/34910/4

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has removed Patrick Rudolph from this change.  ( https://review.coreboot.org/c/coreboot/+/34910 )

Change subject: intel/baytrail: Reorganize romstage.c
......................................................................

Removed reviewer Patrick Rudolph.

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has removed build bot (Jenkins) from this change.  ( https://review.coreboot.org/c/coreboot/+/34910 )

Change subject: intel/baytrail: Reorganize romstage.c
......................................................................

Removed reviewer build bot (Jenkins) with the following votes:

* Verified+1 by build bot (Jenkins)

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34910 )

Change subject: intel/baytrail: Reorganize romstage.c
......................................................................

Patch Set 6: Code-Review+2

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/34910 )

Change subject: intel/baytrail: Reorganize romstage.c
......................................................................

intel/baytrail: Reorganize romstage.c

Done just for future review convenience.

Change-Id: I9cfb0a8177c8ca18947ef0109550a36aa4333383
Signed-off-by: Kyösti Mälkki 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34910
Reviewed-by: Angel Pons 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/baytrail/romstage/romstage.c
1 file changed, 58 insertions(+), 58 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Angel Pons: Looks good to me, approved

diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index aa9fa6b..3607e6d 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -44,16 +44,6 @@
 #include <soc/smm.h>
 #include <soc/spi.h>

-/* The cache-as-ram assembly file calls romstage_main() after setting up
- * cache-as-ram.  romstage_main() will then call the mainboards's
- * mainboard_romstage_entry() function. That function then calls
- * romstage_common() below. The reason for the back and forth is to provide
- * common entry point from cache-as-ram while still allowing for code sharing.
- * Because we can't use global variables the stack is used for allocations --
- * thus the need to call back and forth. */
-
-static struct postcar_frame early_mtrrs;
-
 static void program_base_addresses(void)
 {
    uint32_t reg;
@@ -99,54 +89,6 @@
    write32(bcr, reg);
 }

-/* Entry from cache-as-ram.inc. */
-static void romstage_main(uint64_t tsc)
-{
-	struct romstage_params rp = {
-		.mrc_params = NULL,
-	};
-
-	/* Save initial timestamp from bootblock. */
-	timestamp_init(tsc);
-
-	/* Save romstage begin */
-	timestamp_add_now(TS_START_ROMSTAGE);
-
-	program_base_addresses();
-
-	tco_disable();
-
-	if (CONFIG(ENABLE_BUILTIN_COM1))
-		byt_config_com1_and_enable();
-
-	console_init();
-
-	spi_init();
-
-	set_max_freq();
-
-	punit_init();
-
-	gfx_init();
-
-	/* Call into mainboard. */
-	mainboard_romstage_entry_rp(&rp);
-
-	if (CONFIG(SMM_TSEG))
-		smm_list_regions();
-
-	prepare_and_run_postcar(&early_mtrrs);
-	/* We do not return here. */
-}
-
-/* This wrapper enables easy transition towards C_ENVIRONMENT_BOOTBLOCK,
- * keeping changes in cache_as_ram.S easy to manage.
- */
-asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist)
-{
-	romstage_main(base_timestamp);
-}
-
 static struct chipset_power_state power_state;

static void migrate_power_state(int is_recovery)
@@ -216,6 +158,56 @@
    return prev_sleep_state;
 }

+/* The cache-as-ram assembly file calls romstage_main() after setting up
+ * cache-as-ram.  romstage_main() will then call the mainboards's
+ * mainboard_romstage_entry() function. That function then calls
+ * romstage_common() below. The reason for the back and forth is to provide
+ * common entry point from cache-as-ram while still allowing for code sharing.
+ * Because we can't use global variables the stack is used for allocations --
+ * thus the need to call back and forth. */
+
+static struct postcar_frame early_mtrrs;
+
+/* Entry from cache-as-ram.inc. */
+static void romstage_main(uint64_t tsc)
+{
+	struct romstage_params rp = {
+		.mrc_params = NULL,
+	};
+
+	/* Save initial timestamp from bootblock. */
+	timestamp_init(tsc);
+
+	/* Save romstage begin */
+	timestamp_add_now(TS_START_ROMSTAGE);
+
+	program_base_addresses();
+
+	tco_disable();
+
+	if (CONFIG(ENABLE_BUILTIN_COM1))
+		byt_config_com1_and_enable();
+
+	console_init();
+
+	spi_init();
+
+	set_max_freq();
+
+	punit_init();
+
+	gfx_init();
+
+	/* Call into mainboard. */
+	mainboard_romstage_entry_rp(&rp);
+
+	if (CONFIG(SMM_TSEG))
+		smm_list_regions();
+
+	prepare_and_run_postcar(&early_mtrrs);
+	/* We do not return here. */
+}
+
 /* Entry from the mainboard. */
 void romstage_common(struct romstage_params *params)
 {
@@ -243,6 +235,14 @@
    romstage_handoff_init(prev_sleep_state == ACPI_S3);
 }

+/* This wrapper enables easy transition towards C_ENVIRONMENT_BOOTBLOCK,
+ * keeping changes in cache_as_ram.S easy to manage.
+ */
+asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist)
+{
+	romstage_main(base_timestamp);
+}
+
 void fill_postcar_frame(struct postcar_frame *pcf)
 {
    uintptr_t top_of_ram;