Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38282 )
Change subject: mb/google/dedede: Enable EC ......................................................................
mb/google/dedede: Enable EC
Perform EC initialization in bootblock and ramstages. Add associated ACPI configuration.
BUG=b:144768001 TEST=Build Test.
Change-Id: Ib31ae190818c8870bdd46ea6c3d9ca70dc0485cc Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com --- M src/mainboard/google/dedede/Kconfig M src/mainboard/google/dedede/Makefile.inc M src/mainboard/google/dedede/bootblock.c M src/mainboard/google/dedede/dsdt.asl A src/mainboard/google/dedede/ec.c M src/mainboard/google/dedede/mainboard.c M src/mainboard/google/dedede/smihandler.c A src/mainboard/google/dedede/variants/baseboard/include/baseboard/ec.h A src/mainboard/google/dedede/variants/dedede/include/variant/ec.h 9 files changed, 177 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/38282/1
diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index d824b82..5fe4af5 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -1,5 +1,7 @@ config BOARD_GOOGLE_BASEBOARD_DEDEDE def_bool n + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_ESPI select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select MAINBOARD_HAS_CHROMEOS @@ -14,6 +16,8 @@ config CHROMEOS bool default y + select EC_GOOGLE_CHROMEEC_SWITCHES + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC select VBOOT_LID_SWITCH
config DEVICETREE diff --git a/src/mainboard/google/dedede/Makefile.inc b/src/mainboard/google/dedede/Makefile.inc index 5cb209d..af5cbd1 100644 --- a/src/mainboard/google/dedede/Makefile.inc +++ b/src/mainboard/google/dedede/Makefile.inc @@ -1,4 +1,5 @@ bootblock-y += bootblock.c +bootblock-y += ec.c bootblock-$(CONFIG_CHROMEOS) += chromeos.c
verstage-$(CONFIG_CHROMEOS) += chromeos.c @@ -7,6 +8,7 @@
ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += mainboard.c +ramstage-y += ec.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
diff --git a/src/mainboard/google/dedede/bootblock.c b/src/mainboard/google/dedede/bootblock.c index 04658b4..0a8aa0e 100644 --- a/src/mainboard/google/dedede/bootblock.c +++ b/src/mainboard/google/dedede/bootblock.c @@ -9,6 +9,7 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> #include <bootblock_common.h> +#include <ec/ec.h> #include <soc/gpio.h>
void bootblock_mainboard_init(void) @@ -18,4 +19,5 @@
pads = variant_early_gpio_table(&num); gpio_configure_pads(pads, num); + mainboard_ec_init(); } diff --git a/src/mainboard/google/dedede/dsdt.asl b/src/mainboard/google/dedede/dsdt.asl index 73c11e9..d1cd618 100644 --- a/src/mainboard/google/dedede/dsdt.asl +++ b/src/mainboard/google/dedede/dsdt.asl @@ -41,4 +41,12 @@ /* Chipset specific sleep states */ #include <southbridge/intel/common/acpi/sleepstates.asl>
+ /* Chrome OS Embedded Controller */ + Scope (_SB.PCI0.LPCB) + { + /* ACPI code for EC SuperIO functions */ + #include <ec/google/chromeec/acpi/superio.asl> + /* ACPI code for EC functions */ + #include <ec/google/chromeec/acpi/ec.asl> + } } diff --git a/src/mainboard/google/dedede/ec.c b/src/mainboard/google/dedede/ec.c new file mode 100644 index 0000000..c1ca329 --- /dev/null +++ b/src/mainboard/google/dedede/ec.c @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include <arch/acpi.h> +#include <console/console.h> +#include <ec/ec.h> +#include <ec/google/chromeec/ec.h> +#include <intelblocks/lpc_lib.h> +#include <variant/ec.h> + +static void ramstage_ec_init(void) +{ + static const struct google_chromeec_event_info info = { + .log_events = MAINBOARD_EC_LOG_EVENTS, + .sci_events = MAINBOARD_EC_SCI_EVENTS, + .s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS, + .s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS, + .s0ix_wake_events = MAINBOARD_EC_S0IX_WAKE_EVENTS, + }; + + printk(BIOS_ERR, "mainboard: EC init\n"); + + google_chromeec_events_init(&info, acpi_is_wakeup_s3()); +} + +static void bootblock_ec_init(void) +{ + uint16_t ec_ioport_base; + size_t ec_ioport_size; + + /* + * Set up LPC decoding for the ChromeEC I/O port ranges: + * - Ports 62/66, 60/64, and 200->208 + * - ChromeEC specific communication I/O ports. + */ + lpc_enable_fixed_io_ranges(LPC_IOE_EC_62_66 | LPC_IOE_KBC_60_64 + | LPC_IOE_LGE_200); + google_chromeec_ioport_range(&ec_ioport_base, &ec_ioport_size); + lpc_open_pmio_window(ec_ioport_base, ec_ioport_size); +} + +void mainboard_ec_init(void) +{ + if (ENV_RAMSTAGE) + ramstage_ec_init(); + else if (ENV_BOOTBLOCK) + bootblock_ec_init(); +} diff --git a/src/mainboard/google/dedede/mainboard.c b/src/mainboard/google/dedede/mainboard.c index e22c36a..f045bc7 100644 --- a/src/mainboard/google/dedede/mainboard.c +++ b/src/mainboard/google/dedede/mainboard.c @@ -10,6 +10,7 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> #include <device/device.h> +#include <ec/ec.h> #include <soc/gpio.h> #include <variant/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> @@ -21,6 +22,8 @@
pads = variant_gpio_table(&num); gpio_configure_pads(pads, num); + + mainboard_ec_init(); }
static unsigned long mainboard_write_acpi_tables( diff --git a/src/mainboard/google/dedede/smihandler.c b/src/mainboard/google/dedede/smihandler.c index d4d9c65..eb5508e 100644 --- a/src/mainboard/google/dedede/smihandler.c +++ b/src/mainboard/google/dedede/smihandler.c @@ -9,13 +9,16 @@ #include <arch/acpi.h> #include <baseboard/variants.h> #include <cpu/x86/smm.h> +#include <ec/google/chromeec/smm.h> #include <intelblocks/smihandler.h> #include <soc/pm.h> #include <soc/gpio.h> +#include <variant/ec.h> #include <variant/gpio.h>
void mainboard_smi_gpi_handler(const struct gpi_status *sts) { + /* TODO: Process SMI events from GPI */ }
void mainboard_smi_sleep(u8 slp_typ) @@ -25,9 +28,14 @@
pads = variant_sleep_gpio_table(&num); gpio_configure_pads(pads, num); + + chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, + MAINBOARD_EC_S5_WAKE_EVENTS); }
int mainboard_smi_apmc(u8 apmc) { + chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, + MAINBOARD_EC_SMI_EVENTS); return 0; } diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/ec.h new file mode 100644 index 0000000..3b7577d --- /dev/null +++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/ec.h @@ -0,0 +1,83 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef BASEBOARD_EC_H +#define BASEBOARD_EC_H + +#include <ec/google/chromeec/ec_commands.h> + +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) + +#define MAINBOARD_EC_SMI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) + +/* EC can wake from S5 with lid or power button */ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) + +/* + * EC can wake from S3/S0ix with: + * 1. Lid open + * 2. Power button + * 3. Key press + * 4. Mode change + */ +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (MAINBOARD_EC_S5_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) + +#define MAINBOARD_EC_S0IX_WAKE_EVENTS (MAINBOARD_EC_S3_WAKE_EVENTS) + +/* Log EC wake events plus EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN)|\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) + +/* + * ACPI related definitions for ASL code. + */ + +/* Enable EC backed ALS device in ACPI */ +#define EC_ENABLE_ALS_DEVICE + +/* Enable LID switch and provide wake pin for EC */ +#define EC_ENABLE_LID_SWITCH +#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE + +/* Enable Tablet switch */ +#define EC_ENABLE_TBMC_DEVICE + +/* Enable EC backed PD MCU device in ACPI */ +#define EC_ENABLE_PD_MCU_DEVICE + +#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ +#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ +#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ + +/* Enable EC sync interrupt, EC_SYNC_IRQ is defined in baseboard/gpio.h */ +#define EC_ENABLE_SYNC_IRQ + +#endif diff --git a/src/mainboard/google/dedede/variants/dedede/include/variant/ec.h b/src/mainboard/google/dedede/variants/dedede/include/variant/ec.h new file mode 100644 index 0000000..cc897dc --- /dev/null +++ b/src/mainboard/google/dedede/variants/dedede/include/variant/ec.h @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <baseboard/ec.h> + +#endif
Hello Justin TerAvest, build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38282
to look at the new patch set (#3).
Change subject: mb/google/dedede: Enable EC ......................................................................
mb/google/dedede: Enable EC
Perform EC initialization in bootblock and ramstages. Add associated ACPI configuration.
BUG=b:144768001 TEST=Build Test.
Change-Id: Ib31ae190818c8870bdd46ea6c3d9ca70dc0485cc Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com --- M src/mainboard/google/dedede/Kconfig M src/mainboard/google/dedede/Makefile.inc M src/mainboard/google/dedede/bootblock.c M src/mainboard/google/dedede/chromeos.c M src/mainboard/google/dedede/dsdt.asl A src/mainboard/google/dedede/ec.c M src/mainboard/google/dedede/mainboard.c M src/mainboard/google/dedede/smihandler.c A src/mainboard/google/dedede/variants/baseboard/include/baseboard/ec.h M src/mainboard/google/dedede/variants/baseboard/include/baseboard/gpio.h A src/mainboard/google/dedede/variants/dedede/include/variant/ec.h 11 files changed, 184 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/38282/3
Hello Justin TerAvest, build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38282
to look at the new patch set (#4).
Change subject: mb/google/dedede: Enable EC ......................................................................
mb/google/dedede: Enable EC
Perform EC initialization in bootblock and ramstages. Add associated ACPI configuration.
BUG=b:144768001 TEST=Build Test.
Change-Id: Ib31ae190818c8870bdd46ea6c3d9ca70dc0485cc Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com --- M src/mainboard/google/dedede/Kconfig M src/mainboard/google/dedede/Makefile.inc M src/mainboard/google/dedede/bootblock.c M src/mainboard/google/dedede/chromeos.c M src/mainboard/google/dedede/dsdt.asl A src/mainboard/google/dedede/ec.c M src/mainboard/google/dedede/mainboard.c M src/mainboard/google/dedede/smihandler.c A src/mainboard/google/dedede/variants/baseboard/include/baseboard/ec.h M src/mainboard/google/dedede/variants/baseboard/include/baseboard/gpio.h A src/mainboard/google/dedede/variants/dedede/include/variant/ec.h 11 files changed, 184 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/38282/4
Hello Justin TerAvest, build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38282
to look at the new patch set (#5).
Change subject: mb/google/dedede: Enable EC ......................................................................
mb/google/dedede: Enable EC
Perform EC initialization in bootblock and ramstages. Add associated ACPI configuration.
BUG=b:144768001 TEST=Build Test.
Change-Id: Ib31ae190818c8870bdd46ea6c3d9ca70dc0485cc Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com --- M src/mainboard/google/dedede/Kconfig M src/mainboard/google/dedede/Makefile.inc M src/mainboard/google/dedede/bootblock.c M src/mainboard/google/dedede/chromeos.c M src/mainboard/google/dedede/dsdt.asl A src/mainboard/google/dedede/ec.c M src/mainboard/google/dedede/mainboard.c M src/mainboard/google/dedede/smihandler.c A src/mainboard/google/dedede/variants/baseboard/include/baseboard/ec.h M src/mainboard/google/dedede/variants/baseboard/include/baseboard/gpio.h A src/mainboard/google/dedede/variants/dedede/include/variant/ec.h 11 files changed, 184 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/38282/5
Hello Justin TerAvest, build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38282
to look at the new patch set (#7).
Change subject: mb/google/dedede: Enable EC ......................................................................
mb/google/dedede: Enable EC
Perform EC initialization in bootblock and ramstages. Add associated ACPI configuration.
BUG=b:144768001 TEST=Build Test.
Change-Id: Ib31ae190818c8870bdd46ea6c3d9ca70dc0485cc Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com --- M src/mainboard/google/dedede/Kconfig M src/mainboard/google/dedede/Makefile.inc M src/mainboard/google/dedede/bootblock.c M src/mainboard/google/dedede/chromeos.c M src/mainboard/google/dedede/dsdt.asl A src/mainboard/google/dedede/ec.c M src/mainboard/google/dedede/mainboard.c M src/mainboard/google/dedede/smihandler.c A src/mainboard/google/dedede/variants/baseboard/include/baseboard/ec.h M src/mainboard/google/dedede/variants/baseboard/include/baseboard/gpio.h A src/mainboard/google/dedede/variants/dedede/include/variant/ec.h 11 files changed, 184 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/38282/7
Hello Balaji Manigandan, Aamir Bohra, Justin TerAvest, build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38282
to look at the new patch set (#8).
Change subject: mb/google/dedede: Enable EC ......................................................................
mb/google/dedede: Enable EC
Perform EC initialization in bootblock and ramstages. Add associated ACPI configuration.
BUG=b:144768001 TEST=Build Test.
Change-Id: Ib31ae190818c8870bdd46ea6c3d9ca70dc0485cc Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com --- M src/mainboard/google/dedede/Kconfig M src/mainboard/google/dedede/Makefile.inc M src/mainboard/google/dedede/bootblock.c M src/mainboard/google/dedede/chromeos.c M src/mainboard/google/dedede/dsdt.asl A src/mainboard/google/dedede/ec.c M src/mainboard/google/dedede/mainboard.c M src/mainboard/google/dedede/smihandler.c A src/mainboard/google/dedede/variants/baseboard/include/baseboard/ec.h M src/mainboard/google/dedede/variants/baseboard/include/baseboard/gpio.h A src/mainboard/google/dedede/variants/dedede/include/variant/ec.h 11 files changed, 184 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/38282/8
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38282 )
Change subject: mb/google/dedede: Enable EC ......................................................................
Patch Set 8:
(3 comments)
https://review.coreboot.org/c/coreboot/+/38282/8/src/mainboard/google/dedede... File src/mainboard/google/dedede/Kconfig:
https://review.coreboot.org/c/coreboot/+/38282/8/src/mainboard/google/dedede... PS8, Line 3: EC_ACPI Why is this required?
https://review.coreboot.org/c/coreboot/+/38282/8/src/mainboard/google/dedede... File src/mainboard/google/dedede/ec.c:
https://review.coreboot.org/c/coreboot/+/38282/8/src/mainboard/google/dedede... PS8, Line 31: bootblock_ec_init I don't think this function will be required. The port programming is already done as part of soc/intel/tigerlake and soc/intel/common.
https://review.coreboot.org/c/coreboot/+/38282/8/src/mainboard/google/dedede... File src/mainboard/google/dedede/mainboard.c:
https://review.coreboot.org/c/coreboot/+/38282/8/src/mainboard/google/dedede... PS8, Line 23: mainboard_ec_init In the past, this has been done in the dev->init instead of chip->init. See hatch as example.
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38282 )
Change subject: mb/google/dedede: Enable EC ......................................................................
Patch Set 8:
(3 comments)
https://review.coreboot.org/c/coreboot/+/38282/8/src/mainboard/google/dedede... File src/mainboard/google/dedede/Kconfig:
https://review.coreboot.org/c/coreboot/+/38282/8/src/mainboard/google/dedede... PS8, Line 3: EC_ACPI
Why is this required?
My bad. Not required.
https://review.coreboot.org/c/coreboot/+/38282/8/src/mainboard/google/dedede... File src/mainboard/google/dedede/ec.c:
https://review.coreboot.org/c/coreboot/+/38282/8/src/mainboard/google/dedede... PS8, Line 31: bootblock_ec_init
I don't think this function will be required. […]
Sure, will remove it.
https://review.coreboot.org/c/coreboot/+/38282/8/src/mainboard/google/dedede... File src/mainboard/google/dedede/mainboard.c:
https://review.coreboot.org/c/coreboot/+/38282/8/src/mainboard/google/dedede... PS8, Line 23: mainboard_ec_init
In the past, this has been done in the dev->init instead of chip->init. See hatch as example.
Just curious if there is a dependency reason that it moved to dev->init because in octopus it was done in chip->init.
Hello Balaji Manigandan, Aamir Bohra, Justin TerAvest, build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38282
to look at the new patch set (#9).
Change subject: mb/google/dedede: Enable EC ......................................................................
mb/google/dedede: Enable EC
Perform EC initialization in bootblock and ramstages. Add associated ACPI configuration.
BUG=b:144768001 TEST=Build Test.
Change-Id: Ib31ae190818c8870bdd46ea6c3d9ca70dc0485cc Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com --- M src/mainboard/google/dedede/Kconfig M src/mainboard/google/dedede/Makefile.inc M src/mainboard/google/dedede/bootblock.c M src/mainboard/google/dedede/chromeos.c M src/mainboard/google/dedede/dsdt.asl A src/mainboard/google/dedede/ec.c M src/mainboard/google/dedede/mainboard.c M src/mainboard/google/dedede/smihandler.c A src/mainboard/google/dedede/variants/baseboard/include/baseboard/ec.h M src/mainboard/google/dedede/variants/baseboard/include/baseboard/gpio.h A src/mainboard/google/dedede/variants/dedede/include/variant/ec.h 11 files changed, 169 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/38282/9
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38282 )
Change subject: mb/google/dedede: Enable EC ......................................................................
Patch Set 9:
(3 comments)
https://review.coreboot.org/c/coreboot/+/38282/8/src/mainboard/google/dedede... File src/mainboard/google/dedede/Kconfig:
https://review.coreboot.org/c/coreboot/+/38282/8/src/mainboard/google/dedede... PS8, Line 3: EC_ACPI
My bad. Not required.
I had some compilation error while building dsdt.asl with ec/google/chromeos/acpi/ec.asl included. I tried out different options to fix that compilation error and EC_ACPI is one of them. Finally the issue turned out to be not including the variants/ec.h header file in dsdt.asl. In the process, I forgot to remove this config. Thanks for catching it.
https://review.coreboot.org/c/coreboot/+/38282/8/src/mainboard/google/dedede... File src/mainboard/google/dedede/ec.c:
https://review.coreboot.org/c/coreboot/+/38282/8/src/mainboard/google/dedede... PS8, Line 31: bootblock_ec_init
Sure, will remove it.
Done
https://review.coreboot.org/c/coreboot/+/38282/8/src/mainboard/google/dedede... File src/mainboard/google/dedede/mainboard.c:
https://review.coreboot.org/c/coreboot/+/38282/8/src/mainboard/google/dedede... PS8, Line 23: mainboard_ec_init
Just curious if there is a dependency reason that it moved to dev->init because in octopus it was do […]
Done
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38282 )
Change subject: mb/google/dedede: Enable EC ......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38282/9/src/mainboard/google/dedede... File src/mainboard/google/dedede/ec.c:
https://review.coreboot.org/c/coreboot/+/38282/9/src/mainboard/google/dedede... PS9, Line 33: ENV_RAMSTAGE Now that bootblock doesn't need to call mainboard_ec_init(), I think Makefile can be updated to add ec.c only to ramstage and then this check for ENV_RAMSTAGE can be removed. In fact, all the contents of ramstage_ec_init() can be pulled down here into mainboard_ec_init().
Hello Balaji Manigandan, Aamir Bohra, Justin TerAvest, build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38282
to look at the new patch set (#10).
Change subject: mb/google/dedede: Enable EC ......................................................................
mb/google/dedede: Enable EC
Perform EC initialization in bootblock and ramstages. Add associated ACPI configuration.
BUG=b:144768001 TEST=Build Test.
Change-Id: Ib31ae190818c8870bdd46ea6c3d9ca70dc0485cc Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com --- M src/mainboard/google/dedede/Kconfig M src/mainboard/google/dedede/Makefile.inc M src/mainboard/google/dedede/chromeos.c M src/mainboard/google/dedede/dsdt.asl A src/mainboard/google/dedede/ec.c M src/mainboard/google/dedede/mainboard.c M src/mainboard/google/dedede/smihandler.c A src/mainboard/google/dedede/variants/baseboard/include/baseboard/ec.h M src/mainboard/google/dedede/variants/baseboard/include/baseboard/gpio.h A src/mainboard/google/dedede/variants/dedede/include/variant/ec.h 10 files changed, 160 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/38282/10
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38282 )
Change subject: mb/google/dedede: Enable EC ......................................................................
Patch Set 10:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38282/9/src/mainboard/google/dedede... File src/mainboard/google/dedede/ec.c:
https://review.coreboot.org/c/coreboot/+/38282/9/src/mainboard/google/dedede... PS9, Line 33: ENV_RAMSTAGE
Now that bootblock doesn't need to call mainboard_ec_init(), I think Makefile can be updated to add […]
Done
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38282 )
Change subject: mb/google/dedede: Enable EC ......................................................................
Patch Set 10: Code-Review+2
Furquan Shaikh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38282 )
Change subject: mb/google/dedede: Enable EC ......................................................................
mb/google/dedede: Enable EC
Perform EC initialization in bootblock and ramstages. Add associated ACPI configuration.
BUG=b:144768001 TEST=Build Test.
Change-Id: Ib31ae190818c8870bdd46ea6c3d9ca70dc0485cc Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/38282 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Furquan Shaikh furquan@google.com --- M src/mainboard/google/dedede/Kconfig M src/mainboard/google/dedede/Makefile.inc M src/mainboard/google/dedede/chromeos.c M src/mainboard/google/dedede/dsdt.asl A src/mainboard/google/dedede/ec.c M src/mainboard/google/dedede/mainboard.c M src/mainboard/google/dedede/smihandler.c A src/mainboard/google/dedede/variants/baseboard/include/baseboard/ec.h M src/mainboard/google/dedede/variants/baseboard/include/baseboard/gpio.h A src/mainboard/google/dedede/variants/dedede/include/variant/ec.h 10 files changed, 160 insertions(+), 12 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved
diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index cc7aff6..da6dc81 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -1,5 +1,7 @@ config BOARD_GOOGLE_BASEBOARD_DEDEDE def_bool n + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_ESPI select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select MAINBOARD_HAS_CHROMEOS @@ -14,6 +16,8 @@ config CHROMEOS bool default y + select EC_GOOGLE_CHROMEEC_SWITCHES + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC select VBOOT_LID_SWITCH
config DEVICETREE diff --git a/src/mainboard/google/dedede/Makefile.inc b/src/mainboard/google/dedede/Makefile.inc index 5cb209d..c240ded 100644 --- a/src/mainboard/google/dedede/Makefile.inc +++ b/src/mainboard/google/dedede/Makefile.inc @@ -7,6 +7,7 @@
ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += mainboard.c +ramstage-y += ec.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
diff --git a/src/mainboard/google/dedede/chromeos.c b/src/mainboard/google/dedede/chromeos.c index 44a8c04..dc24f5f 100644 --- a/src/mainboard/google/dedede/chromeos.c +++ b/src/mainboard/google/dedede/chromeos.c @@ -23,18 +23,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); }
-int get_lid_switch(void) -{ - /* TODO: use Chrome EC switches when EC support is added */ - return 1; -} - -int get_recovery_mode_switch(void) -{ - /* TODO: use Chrome EC switches when EC support is added */ - return 0; -} - int get_write_protect_state(void) { /* No write protect */ diff --git a/src/mainboard/google/dedede/dsdt.asl b/src/mainboard/google/dedede/dsdt.asl index 3e278e3..3d17017 100644 --- a/src/mainboard/google/dedede/dsdt.asl +++ b/src/mainboard/google/dedede/dsdt.asl @@ -7,6 +7,7 @@ */
#include <arch/acpi.h> +#include <variant/ec.h> #include <variant/gpio.h>
DefinitionBlock( @@ -41,4 +42,12 @@ /* Chipset specific sleep states */ #include <southbridge/intel/common/acpi/sleepstates.asl>
+ /* Chrome OS Embedded Controller */ + Scope (_SB.PCI0.LPCB) + { + /* ACPI code for EC SuperIO functions */ + #include <ec/google/chromeec/acpi/superio.asl> + /* ACPI code for EC functions */ + #include <ec/google/chromeec/acpi/ec.asl> + } } diff --git a/src/mainboard/google/dedede/ec.c b/src/mainboard/google/dedede/ec.c new file mode 100644 index 0000000..7aa4773 --- /dev/null +++ b/src/mainboard/google/dedede/ec.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include <arch/acpi.h> +#include <console/console.h> +#include <ec/ec.h> +#include <ec/google/chromeec/ec.h> +#include <intelblocks/lpc_lib.h> +#include <variant/ec.h> + +void mainboard_ec_init(void) +{ + static const struct google_chromeec_event_info info = { + .log_events = MAINBOARD_EC_LOG_EVENTS, + .sci_events = MAINBOARD_EC_SCI_EVENTS, + .s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS, + .s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS, + .s0ix_wake_events = MAINBOARD_EC_S0IX_WAKE_EVENTS, + }; + + printk(BIOS_ERR, "mainboard: EC init\n"); + + google_chromeec_events_init(&info, acpi_is_wakeup_s3()); +} diff --git a/src/mainboard/google/dedede/mainboard.c b/src/mainboard/google/dedede/mainboard.c index 64bb5ac..3ac273a 100644 --- a/src/mainboard/google/dedede/mainboard.c +++ b/src/mainboard/google/dedede/mainboard.c @@ -9,6 +9,7 @@ #include <arch/acpi.h> #include <baseboard/variants.h> #include <device/device.h> +#include <ec/ec.h> #include <vendorcode/google/chromeos/chromeos.h>
static void mainboard_init(void *chip_info) @@ -20,6 +21,11 @@ gpio_configure_pads(pads, num); }
+static void mainboard_dev_init(struct device *dev) +{ + mainboard_ec_init(); +} + static unsigned long mainboard_write_acpi_tables( struct device *device, unsigned long current, acpi_rsdp_t *rsdp) { @@ -28,6 +34,7 @@
static void mainboard_enable(struct device *dev) { + dev->ops->init = mainboard_dev_init; dev->ops->write_acpi_tables = mainboard_write_acpi_tables; dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; } diff --git a/src/mainboard/google/dedede/smihandler.c b/src/mainboard/google/dedede/smihandler.c index 780d33f..2c2230f 100644 --- a/src/mainboard/google/dedede/smihandler.c +++ b/src/mainboard/google/dedede/smihandler.c @@ -8,10 +8,13 @@
#include <baseboard/variants.h> #include <cpu/x86/smm.h> +#include <ec/google/chromeec/smm.h> #include <intelblocks/smihandler.h> +#include <variant/ec.h>
void mainboard_smi_gpi_handler(const struct gpi_status *sts) { + /* TODO: Process SMI events from GPI */ }
void mainboard_smi_sleep(u8 slp_typ) @@ -21,9 +24,14 @@
pads = variant_sleep_gpio_table(&num); gpio_configure_pads(pads, num); + + chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, + MAINBOARD_EC_S5_WAKE_EVENTS); }
int mainboard_smi_apmc(u8 apmc) { + chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, + MAINBOARD_EC_SMI_EVENTS); return 0; } diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/ec.h new file mode 100644 index 0000000..2f0024c --- /dev/null +++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/ec.h @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef __BASEBOARD_EC_H__ +#define __BASEBOARD_EC_H__ + +#include <ec/ec.h> +#include <ec/google/chromeec/ec_commands.h> +#include <baseboard/gpio.h> + +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) + +#define MAINBOARD_EC_SMI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) + +/* EC can wake from S5 with lid or power button */ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) + +/* + * EC can wake from S3/S0ix with: + * 1. Lid open + * 2. Power button + * 3. Key press + * 4. Mode change + */ +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (MAINBOARD_EC_S5_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) + +#define MAINBOARD_EC_S0IX_WAKE_EVENTS (MAINBOARD_EC_S3_WAKE_EVENTS) + +/* Log EC wake events plus EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) + +/* + * ACPI related definitions for ASL code. + */ + +/* Enable EC backed ALS device in ACPI */ +#define EC_ENABLE_ALS_DEVICE + +/* Enable LID switch and provide wake pin for EC */ +#define EC_ENABLE_LID_SWITCH +#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE + +/* Enable Tablet switch */ +#define EC_ENABLE_TBMC_DEVICE + +/* Enable EC backed PD MCU device in ACPI */ +#define EC_ENABLE_PD_MCU_DEVICE + +#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ +#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ +#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ + +#endif /* __BASEBOARD_EC_H__ */ diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/gpio.h index 55faf01..fe9c0c5 100644 --- a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/gpio.h @@ -12,4 +12,10 @@ #include <soc/gpe.h> #include <soc/gpio.h>
+/* eSPI virtual wire reporting */ +#define EC_SCI_GPI GPE0_ESPI + +/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ +#define GPE_EC_WAKE GPE0_LAN_WAK + #endif /* __BASEBOARD_GPIO_H__ */ diff --git a/src/mainboard/google/dedede/variants/dedede/include/variant/ec.h b/src/mainboard/google/dedede/variants/dedede/include/variant/ec.h new file mode 100644 index 0000000..cc897dc --- /dev/null +++ b/src/mainboard/google/dedede/variants/dedede/include/variant/ec.h @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <baseboard/ec.h> + +#endif
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38282 )
Change subject: mb/google/dedede: Enable EC ......................................................................
Patch Set 12:
Automatic boot test returned (PASS/FAIL/TOTAL): 3/0/3 Emulation targets: EMULATION_QEMU_X86_Q35 using payload TianoCore : SUCCESS : https://lava.9esec.io/r/298 EMULATION_QEMU_X86_Q35 using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/297 EMULATION_QEMU_X86_I440FX using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/296
Please note: This test is under development and might not be accurate at all!
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9elements QA (Code Review) -
Furquan Shaikh (Code Review)
-
Karthik Ramasubramanian (Code Review)