Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48397 )
Change subject: nb/intel/sandybridge: Add comments about I/O and RT latency ......................................................................
nb/intel/sandybridge: Add comments about I/O and RT latency
Document the algorithm to adjust I/O and roundtrip latencies.
Change-Id: Ic8b9aed54a34bb3252c457e87e81387fd410e305 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 21 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/48397/1
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 0618af9..2dc7520 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1060,6 +1060,7 @@ { wait_for_iosav(channel);
+ /* Send a burst of 16 back-to-back read commands (4 DCLK apart) */ iosav_write_read_mpr_sequence(channel, slotrank, ctrl->tMOD, 1, 3, 15, ctrl->CAS + 36);
/* Execute command queue */ @@ -1194,6 +1195,12 @@ } }
+/* + * Once the DQS high phase has been found (for each DRAM) the next stage + * is to find out the round trip latency, by locating the preamble cycle. + * This is achieved by trying smaller and smaller roundtrip values until + * the strobe sampling is done on the preamble cycle. + */ static int find_roundtrip_latency(ramctr_timing *ctrl, int channel, int slotrank, int *upperA) { int works[NUM_LANES]; @@ -1213,10 +1220,17 @@ else all_works = 0; } + + /* If every lane is working, exit */ if (all_works) return 0;
+ /* + * If all bits are one (everyone is failing), decrement + * the roundtrip value by two, and do another iteration. + */ if (!some_works) { + /* Guard against roundtrip latency underflow */ if (ctrl->timings[channel][slotrank].roundtrip_latency < 2) { printk(BIOS_EMERG, "402x discovery failed (1): %d, %d\n", channel, slotrank); @@ -1226,9 +1240,16 @@ printram("4024 -= 2;\n"); continue; } + + /* + * Else (if some lanes are failing), increase the rank's + * I/O latency by 2, and increase rcven logic delay by 2 + * on the working lanes, then perform another iteration. + */ ctrl->timings[channel][slotrank].io_latency += 2; printram("4028 += 2;\n");
+ /* Guard against I/O latency overflow */ if (ctrl->timings[channel][slotrank].io_latency >= 0x10) { printk(BIOS_EMERG, "402x discovery failed (2): %d, %d\n", channel, slotrank);
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48397 )
Change subject: nb/intel/sandybridge: Add comments about I/O and RT latency ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48397/5/src/northbridge/intel/sandy... File src/northbridge/intel/sandybridge/raminit_common.c:
https://review.coreboot.org/c/coreboot/+/48397/5/src/northbridge/intel/sandy... PS5, Line 1252: /* Guard against I/O latency overflow */ Could that be added to the emergency log message?
I/O latency overflow: 402x discovery failed (2): %d, %d\n
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48397 )
Change subject: nb/intel/sandybridge: Add comments about I/O and RT latency ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48397/5/src/northbridge/intel/sandy... File src/northbridge/intel/sandybridge/raminit_common.c:
https://review.coreboot.org/c/coreboot/+/48397/5/src/northbridge/intel/sandy... PS5, Line 1252: /* Guard against I/O latency overflow */
Could that be added to the emergency log message? […]
I've improved these messages in CB:48601
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48397 )
Change subject: nb/intel/sandybridge: Add comments about I/O and RT latency ......................................................................
Patch Set 7: Code-Review+2
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48397 )
Change subject: nb/intel/sandybridge: Add comments about I/O and RT latency ......................................................................
nb/intel/sandybridge: Add comments about I/O and RT latency
Document the algorithm to adjust I/O and roundtrip latencies.
Change-Id: Ic8b9aed54a34bb3252c457e87e81387fd410e305 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/48397 Reviewed-by: Patrick Rudolph siro@das-labor.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 21 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index d24e5a8..70a856c 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1059,6 +1059,7 @@ { wait_for_iosav(channel);
+ /* Send a burst of 16 back-to-back read commands (4 DCLK apart) */ iosav_write_read_mpr_sequence(channel, slotrank, ctrl->tMOD, 1, 3, 15, ctrl->CAS + 36);
/* Execute command queue */ @@ -1193,6 +1194,12 @@ } }
+/* + * Once the DQS high phase has been found (for each DRAM) the next stage + * is to find out the round trip latency, by locating the preamble cycle. + * This is achieved by trying smaller and smaller roundtrip values until + * the strobe sampling is done on the preamble cycle. + */ static int find_roundtrip_latency(ramctr_timing *ctrl, int channel, int slotrank, int *upperA) { int works[NUM_LANES]; @@ -1212,10 +1219,17 @@ else all_works = 0; } + + /* If every lane is working, exit */ if (all_works) return 0;
+ /* + * If all bits are one (everyone is failing), decrement + * the roundtrip value by two, and do another iteration. + */ if (!some_works) { + /* Guard against roundtrip latency underflow */ if (ctrl->timings[channel][slotrank].roundtrip_latency < 2) { printk(BIOS_EMERG, "402x discovery failed (1): %d, %d\n", channel, slotrank); @@ -1225,9 +1239,16 @@ printram("4024 -= 2;\n"); continue; } + + /* + * Else (if some lanes are failing), increase the rank's + * I/O latency by 2, and increase rcven logic delay by 2 + * on the working lanes, then perform another iteration. + */ ctrl->timings[channel][slotrank].io_latency += 2; printram("4028 += 2;\n");
+ /* Guard against I/O latency overflow */ if (ctrl->timings[channel][slotrank].io_latency >= 0x10) { printk(BIOS_EMERG, "402x discovery failed (2): %d, %d\n", channel, slotrank);
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Angel Pons (Code Review) -
Felix Held (Code Review)
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Patrick Rudolph (Code Review)
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Paul Menzel (Code Review)