[M] Change in coreboot[master]: soc/intel/alderlake: Add/Remove LTR disqualification for UFS

[Reka Norman (Code Review)]

Attention is currently required from: Haribalaraman Ramasubramanian, Rizwan Qureshi, Tim Wawrzynczak, Daniil Lunev, Meera Ravindranath, Divagar Mohandass.

Reka Norman has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68251 )

Change subject: soc/intel/alderlake: Add/Remove LTR disqualification for UFS
......................................................................

Patch Set 6:

(2 comments)

File src/soc/intel/alderlake/include/soc/ufs.h:

https://review.coreboot.org/c/coreboot/+/68251/comment/ed7c2399_903b7484 
PS6, Line 26: R_PMC_PWRM_LTR_IGN
Is this in the EDS? I can't see it.

https://review.coreboot.org/c/coreboot/+/68251/comment/4f6c37e0_320be99a 
PS6, Line 27: PCH_PWRM_BASE_SIZE
This is redefining a macro from iomap.h. Should it be called something else?

And I don't quite understand what it's doing. Why are you only mapping the region up to 0x1E30 - where does the value 0x1E30 come from?