Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/29060 )
Change subject: vboot: fix CONFIG_RESUME_PATH_SAME_AS_BOOT S3 resume logic ......................................................................
vboot: fix CONFIG_RESUME_PATH_SAME_AS_BOOT S3 resume logic
- should not check VBOOT_STARTS_IN_BOOTBLOCK to set context flag - implement vboot_platform_is_resuming on platforms missing it - add ACPI_INTEL_HARDWARE_SLEEP_VALUES to two intel southbridges
[ originally https://review.coreboot.org/c/coreboot/+/28750 ]
BUG=b:114018226 TEST=compile coreboot
Change-Id: I1ef0bcdfd01746198f8140f49698b58065d820b9 Signed-off-by: Joel Kitching kitching@google.com Reviewed-on: https://review.coreboot.org/29060 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Aaron Durbin adurbin@chromium.org Reviewed-by: Philipp Deppenwiese zaolin.daisuki@gmail.com --- M src/security/vboot/vboot_logic.c M src/soc/intel/baytrail/pmutil.c M src/soc/intel/braswell/pmutil.c M src/soc/intel/broadwell/pmutil.c M src/soc/intel/fsp_baytrail/romstage/romstage.c M src/southbridge/intel/common/pmbase.c M src/southbridge/intel/common/pmutil.h M src/southbridge/intel/i82371eb/Kconfig M src/southbridge/intel/i82801jx/Kconfig 9 files changed, 53 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Aaron Durbin: Looks good to me, approved Philipp Deppenwiese: Looks good to me, approved
diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index f3a6b41..1b24160 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -309,7 +309,6 @@ * does verification of memory init and thus must ensure it resumes with * the same slot that it booted from. */ if (IS_ENABLED(CONFIG_RESUME_PATH_SAME_AS_BOOT) && - IS_ENABLED(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK) && vboot_platform_is_resuming()) ctx.flags |= VB2_CONTEXT_S3_RESUME;
diff --git a/src/soc/intel/baytrail/pmutil.c b/src/soc/intel/baytrail/pmutil.c index 51c3ea0..06751f1 100644 --- a/src/soc/intel/baytrail/pmutil.c +++ b/src/soc/intel/baytrail/pmutil.c @@ -14,6 +14,7 @@ */
#include <stdint.h> +#include <arch/acpi.h> #include <arch/io.h> #include <cbmem.h> #include <console/console.h> @@ -23,6 +24,7 @@ #include <soc/pci_devs.h> #include <soc/pmc.h> #include <security/vboot/vbnv.h> +#include <security/vboot/vboot_common.h>
#if defined(__SIMPLE_DEVICE__)
@@ -384,3 +386,11 @@ { return rtc_failure(); } + +int vboot_platform_is_resuming(void) +{ + if (!(inw(ACPI_BASE_ADDRESS + PM1_STS) & WAK_STS)) + return 0; + + return acpi_sleep_from_pm1(inl(ACPI_BASE_ADDRESS + PM1_CNT)) == ACPI_S3; +} diff --git a/src/soc/intel/braswell/pmutil.c b/src/soc/intel/braswell/pmutil.c index 00284d1..85384a61 100644 --- a/src/soc/intel/braswell/pmutil.c +++ b/src/soc/intel/braswell/pmutil.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */
+#include <arch/acpi.h> #include <arch/io.h> #include <cbmem.h> #include <console/console.h> @@ -24,6 +25,7 @@ #include <soc/pm.h> #include <stdint.h> #include <security/vboot/vbnv.h> +#include <security/vboot/vboot_common.h>
#if defined(__SIMPLE_DEVICE__)
@@ -380,3 +382,11 @@ { return rtc_failure(); } + +int vboot_platform_is_resuming(void) +{ + if (!(inw(ACPI_BASE_ADDRESS + PM1_STS) & WAK_STS)) + return 0; + + return acpi_sleep_from_pm1(inl(ACPI_BASE_ADDRESS + PM1_CNT)) == ACPI_S3; +} diff --git a/src/soc/intel/broadwell/pmutil.c b/src/soc/intel/broadwell/pmutil.c index 3899130..e19025b 100644 --- a/src/soc/intel/broadwell/pmutil.c +++ b/src/soc/intel/broadwell/pmutil.c @@ -18,6 +18,7 @@ * and the differences between PCH variants. */
+#include <arch/acpi.h> #include <arch/io.h> #include <device/device.h> #include <device/pci.h> @@ -29,6 +30,7 @@ #include <soc/pm.h> #include <soc/gpio.h> #include <security/vboot/vbnv.h> +#include <security/vboot/vboot_common.h>
/* Print status bits with descriptive names */ static void print_status_bits(u32 status, const char *bit_names[]) @@ -473,3 +475,11 @@ { return rtc_failure(); } + +int vboot_platform_is_resuming(void) +{ + if (!(inw(ACPI_BASE_ADDRESS + PM1_STS) & WAK_STS)) + return 0; + + return acpi_sleep_from_pm1(inl(ACPI_BASE_ADDRESS + PM1_CNT)) == ACPI_S3; +} diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c index f8d985e..fb5962e 100644 --- a/src/soc/intel/fsp_baytrail/romstage/romstage.c +++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c @@ -39,6 +39,7 @@ #include <version.h> #include <pc80/mc146818rtc.h> #include <device/pci_def.h> +#include <security/vboot/vboot_common.h>
/* Return 0, 3, 4 or 5 to indicate the previous sleep state. */ uint32_t chipset_prev_sleep_state(uint32_t clear) @@ -271,3 +272,8 @@ { return 0; } + +int vboot_platform_is_resuming(void) +{ + return !!romstage_handoff_is_resume(); +} diff --git a/src/southbridge/intel/common/pmbase.c b/src/southbridge/intel/common/pmbase.c index 360b63d..2de57d6 100644 --- a/src/southbridge/intel/common/pmbase.c +++ b/src/southbridge/intel/common/pmbase.c @@ -14,13 +14,16 @@ */
#include <stdint.h> +#include <arch/acpi.h> #include <arch/io.h> #include <device/device.h> #include <device/pci.h> #include <arch/early_variables.h> #include <assert.h> +#include <security/vboot/vboot_common.h>
#include "pmbase.h" +#include "pmutil.h"
/* LPC PM Base Address Register */ #define PMBASE 0x40 @@ -91,3 +94,13 @@
return inb(lpc_get_pmbase() + addr); } + +int vboot_platform_is_resuming(void) +{ + u16 reg16 = read_pmbase16(PM1_STS); + + if (!(reg16 & WAK_STS)) + return 0; + + return acpi_sleep_from_pm1(reg16) == ACPI_S3; +} diff --git a/src/southbridge/intel/common/pmutil.h b/src/southbridge/intel/common/pmutil.h index 273e0f8..26134d9 100644 --- a/src/southbridge/intel/common/pmutil.h +++ b/src/southbridge/intel/common/pmutil.h @@ -17,6 +17,8 @@ #ifndef INTEL_COMMON_PMUTIL_H #define INTEL_COMMON_PMUTIL_H
+#include <cpu/x86/smm.h> + #define D31F0_PMBASE 0x40 #define D31F0_GEN_PMCON_3 0xa4 #define D31F0_GPIO_ROUT 0xb8 diff --git a/src/southbridge/intel/i82371eb/Kconfig b/src/southbridge/intel/i82371eb/Kconfig index f22c6e9..6552099 100644 --- a/src/southbridge/intel/i82371eb/Kconfig +++ b/src/southbridge/intel/i82371eb/Kconfig @@ -1,4 +1,5 @@ config SOUTHBRIDGE_INTEL_I82371EB + select ACPI_INTEL_HARDWARE_SLEEP_VALUES select SOUTHBRIDGE_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_SMBUS bool diff --git a/src/southbridge/intel/i82801jx/Kconfig b/src/southbridge/intel/i82801jx/Kconfig index e56d692..4308e29 100644 --- a/src/southbridge/intel/i82801jx/Kconfig +++ b/src/southbridge/intel/i82801jx/Kconfig @@ -28,6 +28,7 @@ select SOUTHBRIDGE_INTEL_COMMON_GPIO select INTEL_DESCRIPTOR_MODE_CAPABLE select COMMON_FADT + select ACPI_INTEL_HARDWARE_SLEEP_VALUES
if SOUTHBRIDGE_INTEL_I82801JX