[XS] Change in coreboot[main]: soc/intel/xeon_xp: Fix lower ram range bug

[Name of user not set (Code Review)]

[e-mail] has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85434?usp=email )

Change subject: soc/intel/xeon_xp: Fix lower ram range bug
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soc/intel/xeon_xp: Fix lower ram range bug

Generally the base address of FSP output is already aligned so there is no
need to minus 1. The current code loses 1 byte in the lower DRAM address
space.

Change-Id: Ia8147702aad496c431cf10b896d68a826c9e45b1
Signed-off-by: Yuchi Chen 
---
M src/soc/intel/xeon_sp/uncore.c
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/85434/1

diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c
index 1d77675..93677b9 100644
--- a/src/soc/intel/xeon_sp/uncore.c
+++ b/src/soc/intel/xeon_sp/uncore.c
@@ -268,7 +268,7 @@

/* 1MB -> top_of_ram */
    fsp_find_reserved_memory(&fsp_mem);
-	top_of_ram = range_entry_base(&fsp_mem) - 1;
+	top_of_ram = range_entry_base(&fsp_mem);
    res = ram_from_to(dev, index++, 1 * MiB, top_of_ram);
    LOG_RESOURCE("low_ram", dev, res);