Change in coreboot[master]: soc/intel/cannonlake: Change mainboard_silicon_init_params argument
Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48644 )
Change subject: soc/intel/cannonlake: Change mainboard_silicon_init_params argument ......................................................................
soc/intel/cannonlake: Change mainboard_silicon_init_params argument
Use FSPS_UPD instead of FSP_S_CONFIG as argument as already done on xeon_sp and denverton_ns. This allows to set test config UPDs from mainboard code as well.
Change-Id: I6d67264e22df32b9210ce88b99d6a7a4f6b97ffb Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/mainboard/prodrive/hermes/ramstage.c M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/cannonlake/include/soc/ramstage.h 3 files changed, 6 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/48644/1
diff --git a/src/mainboard/prodrive/hermes/ramstage.c b/src/mainboard/prodrive/hermes/ramstage.c index b8b147d..72ae014 100644 --- a/src/mainboard/prodrive/hermes/ramstage.c +++ b/src/mainboard/prodrive/hermes/ramstage.c @@ -8,8 +8,10 @@ /* FIXME: Fill with additional options */ };
-void mainboard_silicon_init_params(FSP_S_CONFIG *params) +void mainboard_silicon_init_params(FSPS_UPD *supd) { + FSP_S_CONFIG *params = &supd->FspsConfig; + /* Configure pads prior to SiliconInit() in case there's any dependencies during hardware initialization. */ program_gpio_pads(); diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 9b28d3d..73b1bb5 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -143,7 +143,7 @@ /* Load VBT before devicetree-specific config. */ params->GraphicsConfigPtr = (uintptr_t)vbt_get();
- mainboard_silicon_init_params(params); + mainboard_silicon_init_params(supd);
const struct soc_power_limits_config *soc_config; soc_config = &config->power_limits_config; @@ -527,7 +527,7 @@ }
/* Mainboard GPIO Configuration */ -__weak void mainboard_silicon_init_params(FSP_S_CONFIG *params) +__weak void mainboard_silicon_init_params(FSPS_UPD *supd) { printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); } diff --git a/src/soc/intel/cannonlake/include/soc/ramstage.h b/src/soc/intel/cannonlake/include/soc/ramstage.h index 96b1129..ff4fd59 100644 --- a/src/soc/intel/cannonlake/include/soc/ramstage.h +++ b/src/soc/intel/cannonlake/include/soc/ramstage.h @@ -9,7 +9,7 @@
#include "../../chip.h"
-void mainboard_silicon_init_params(FSP_S_CONFIG *params); +void mainboard_silicon_init_params(FSPS_UPD *supd); void soc_init_pre_device(void *chip_info);
#endif
Hello build bot (Jenkins), Christian Walter, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48644
to look at the new patch set (#2).
Change subject: soc/intel/cannonlake: Change mainboard_silicon_init_params argument ......................................................................
soc/intel/cannonlake: Change mainboard_silicon_init_params argument
Use FSPS_UPD instead of FSP_S_CONFIG as argument as already done on xeon_sp and denverton_ns. This allows to set test config UPDs from mainboard code as well.
Change-Id: I6d67264e22df32b9210ce88b99d6a7a4f6b97ffb Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/mainboard/google/hatch/ramstage.c M src/mainboard/prodrive/hermes/ramstage.c M src/mainboard/purism/librem_cnl/ramstage.c M src/mainboard/system76/lemp9/ramstage.c M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/cannonlake/include/soc/ramstage.h 6 files changed, 9 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/48644/2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48644 )
Change subject: soc/intel/cannonlake: Change mainboard_silicon_init_params argument ......................................................................
Patch Set 2: Code-Review+2
Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48644 )
Change subject: soc/intel/cannonlake: Change mainboard_silicon_init_params argument ......................................................................
Patch Set 2: Code-Review+1
LGTM, makes it consistent with the way romstage is handled too
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48644 )
Change subject: soc/intel/cannonlake: Change mainboard_silicon_init_params argument ......................................................................
Patch Set 2: Code-Review+2
Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48644 )
Change subject: soc/intel/cannonlake: Change mainboard_silicon_init_params argument ......................................................................
soc/intel/cannonlake: Change mainboard_silicon_init_params argument
Use FSPS_UPD instead of FSP_S_CONFIG as argument as already done on xeon_sp and denverton_ns. This allows to set test config UPDs from mainboard code as well.
Change-Id: I6d67264e22df32b9210ce88b99d6a7a4f6b97ffb Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/48644 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com Reviewed-by: Matt DeVillier matt.devillier@gmail.com Reviewed-by: Felix Singer felixsinger@posteo.net --- M src/mainboard/google/hatch/ramstage.c M src/mainboard/prodrive/hermes/ramstage.c M src/mainboard/purism/librem_cnl/ramstage.c M src/mainboard/system76/lemp9/ramstage.c M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/cannonlake/include/soc/ramstage.h 6 files changed, 9 insertions(+), 7 deletions(-)
Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, but someone else must approve Felix Singer: Looks good to me, approved Angel Pons: Looks good to me, approved
diff --git a/src/mainboard/google/hatch/ramstage.c b/src/mainboard/google/hatch/ramstage.c index af88100..93864b2 100644 --- a/src/mainboard/google/hatch/ramstage.c +++ b/src/mainboard/google/hatch/ramstage.c @@ -8,7 +8,7 @@ #include <variant/gpio.h> #include <vendorcode/google/chromeos/chromeos.h>
-void mainboard_silicon_init_params(FSP_S_CONFIG *params) +void mainboard_silicon_init_params(FSPS_UPD *supd) { variant_devtree_update(); } diff --git a/src/mainboard/prodrive/hermes/ramstage.c b/src/mainboard/prodrive/hermes/ramstage.c index b8b147d..72ae014 100644 --- a/src/mainboard/prodrive/hermes/ramstage.c +++ b/src/mainboard/prodrive/hermes/ramstage.c @@ -8,8 +8,10 @@ /* FIXME: Fill with additional options */ };
-void mainboard_silicon_init_params(FSP_S_CONFIG *params) +void mainboard_silicon_init_params(FSPS_UPD *supd) { + FSP_S_CONFIG *params = &supd->FspsConfig; + /* Configure pads prior to SiliconInit() in case there's any dependencies during hardware initialization. */ program_gpio_pads(); diff --git a/src/mainboard/purism/librem_cnl/ramstage.c b/src/mainboard/purism/librem_cnl/ramstage.c index e93911e..381d03b 100644 --- a/src/mainboard/purism/librem_cnl/ramstage.c +++ b/src/mainboard/purism/librem_cnl/ramstage.c @@ -3,7 +3,7 @@ #include <soc/ramstage.h> #include "variant.h"
-void mainboard_silicon_init_params(FSP_S_CONFIG *params) +void mainboard_silicon_init_params(FSPS_UPD *supd) { /* Configure pads prior to SiliconInit() in case there's any * dependencies during hardware initialization. */ diff --git a/src/mainboard/system76/lemp9/ramstage.c b/src/mainboard/system76/lemp9/ramstage.c index 4b0ddd4..35ffd53 100644 --- a/src/mainboard/system76/lemp9/ramstage.c +++ b/src/mainboard/system76/lemp9/ramstage.c @@ -3,7 +3,7 @@ #include <soc/ramstage.h> #include "gpio.h"
-void mainboard_silicon_init_params(FSP_S_CONFIG *params) +void mainboard_silicon_init_params(FSPS_UPD *supd) { /* Configure pads prior to SiliconInit() in case there's any * dependencies during hardware initialization. */ diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 9b28d3d..73b1bb5 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -143,7 +143,7 @@ /* Load VBT before devicetree-specific config. */ params->GraphicsConfigPtr = (uintptr_t)vbt_get();
- mainboard_silicon_init_params(params); + mainboard_silicon_init_params(supd);
const struct soc_power_limits_config *soc_config; soc_config = &config->power_limits_config; @@ -527,7 +527,7 @@ }
/* Mainboard GPIO Configuration */ -__weak void mainboard_silicon_init_params(FSP_S_CONFIG *params) +__weak void mainboard_silicon_init_params(FSPS_UPD *supd) { printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); } diff --git a/src/soc/intel/cannonlake/include/soc/ramstage.h b/src/soc/intel/cannonlake/include/soc/ramstage.h index 96b1129..ff4fd59 100644 --- a/src/soc/intel/cannonlake/include/soc/ramstage.h +++ b/src/soc/intel/cannonlake/include/soc/ramstage.h @@ -9,7 +9,7 @@
#include "../../chip.h"
-void mainboard_silicon_init_params(FSP_S_CONFIG *params); +void mainboard_silicon_init_params(FSPS_UPD *supd); void soc_init_pre_device(void *chip_info);
#endif
-
Angel Pons (Code Review) -
Felix Singer (Code Review)
-
Hung-Te Lin (Code Review)
-
Matt DeVillier (Code Review)
-
Patrick Rudolph (Code Review)