Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85832?usp=email )
Change subject: mb/asus/h61-series: Add P8H67-I DELUXE variant ......................................................................
mb/asus/h61-series: Add P8H67-I DELUXE variant
On vendor firmware, the IFD is read-only and ME completely locked. But the BIOS region can be internally flashed with coreboot. Super I/O GP15 is connected to HDA_SDO, potentially enabling write access to entire flash. Simply setting this GPIO, and restarting the board wasn't enough.
Tested: - i5-2500K - 8GB or 2x8GB Hynix HMT41GS6BFR8A-RD (@1333MHz) - 8+4GB Hynix HMT351S6EFR8A-PB (@1333MHz) - Internal SATA ports - Realtek Ethernet - libgfxinit, onboard DVI - All rear USB and USB3 ports, internal Bluetooth dongle is detected - SeaBIOS boots to Void Linux and Devuan - PS/2 keyboard and mouse (only combo port, one at a time) - PEG slot - Mini-PCIe WLAN slot
Not tested: - eSATA - SPDIF - LEDs: front panel
Not working: - Super I/O shows weird temperatures in lm_sensors: CPU -51°C AUX +84°C - Resuming from S3 when root partition is on an USB 3.0 stick (works when it's attached to USB 2.0 or SATA). - DRAM_LED (on vendor firmware, it stays lit if there are DRAM problems)
Change-Id: I7de37a5cb8bf8d44253fe3418ffc9e07caca9703 Signed-off-by: Riku Viitanen riku.viitanen@protonmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/85832 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Nicholas Chin nic.c3.14@gmail.com --- M src/mainboard/asus/h61-series/Kconfig M src/mainboard/asus/h61-series/Kconfig.name A src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/board_info.txt A src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/cmos.default A src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/cmos.layout A src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/data.vbt A src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/early_init.c A src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/gma-mainboard.ads A src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/gpio.c A src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/hda_verb.c A src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/overridetree.cb 11 files changed, 443 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Nicholas Chin: Looks good to me, approved
diff --git a/src/mainboard/asus/h61-series/Kconfig b/src/mainboard/asus/h61-series/Kconfig index 08e7a22..4c4fd7e 100644 --- a/src/mainboard/asus/h61-series/Kconfig +++ b/src/mainboard/asus/h61-series/Kconfig @@ -60,6 +60,15 @@ select RT8168_SET_LED_MODE select SUPERIO_NUVOTON_NCT6776
+config BOARD_ASUS_P8H67_I_DELUXE + select BOARD_ASUS_H61_SERIES + select BOARD_ROMSIZE_KB_4096 + select HAVE_CMOS_DEFAULT + select HAVE_OPTION_TABLE + select NO_UART_ON_SUPERIO + select REALTEK_8168_RESET + select SUPERIO_NUVOTON_NCT6776 + if BOARD_ASUS_H61_SERIES
config MAINBOARD_DIR @@ -71,6 +80,7 @@ default "p8h61-m_lx3_r2_0" if BOARD_ASUS_P8H61_M_LX3_R2_0 default "p8h61-m_pro" if BOARD_ASUS_P8H61_M_PRO default "p8h61-m_pro_cm6630" if BOARD_ASUS_P8H61_M_PRO_CM6630 + default "p8h67-i_deluxe" if BOARD_ASUS_P8H67_I_DELUXE
config MAINBOARD_PART_NUMBER default "H61M-CS" if BOARD_ASUS_H61M_CS @@ -78,6 +88,7 @@ default "P8H61-M LX3 R2.0" if BOARD_ASUS_P8H61_M_LX3_R2_0 default "P8H61-M PRO" if BOARD_ASUS_P8H61_M_PRO default "P8H61-M PRO CM6630" if BOARD_ASUS_P8H61_M_PRO_CM6630 + default "P8H67-I DELUXE" if BOARD_ASUS_P8H67_I_DELUXE
config OVERRIDE_DEVICETREE default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" @@ -88,6 +99,9 @@ config CMOS_LAYOUT_FILE default "src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/cmos.layout"
+config CBFS_SIZE + default 0x280000 if BOARD_ASUS_P8H67_I_DELUXE + # # These ME partitions need to be whitelisted for correct system # operation. Example issues from removing them include: no serial output diff --git a/src/mainboard/asus/h61-series/Kconfig.name b/src/mainboard/asus/h61-series/Kconfig.name index 6db12b4..eee48c0 100644 --- a/src/mainboard/asus/h61-series/Kconfig.name +++ b/src/mainboard/asus/h61-series/Kconfig.name @@ -14,3 +14,6 @@
config BOARD_ASUS_P8H61_M_PRO_CM6630 bool "P8H61-M PRO CM6630" + +config BOARD_ASUS_P8H67_I_DELUXE + bool "P8H67-I DELUXE" diff --git a/src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/board_info.txt b/src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/board_info.txt new file mode 100644 index 0000000..2bfc9b5 --- /dev/null +++ b/src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/board_info.txt @@ -0,0 +1,9 @@ +Category: desktop +Board URL: https://www.asus.com/us/supportonly/p8h67-i%20deluxe/helpdesk_knowledge/ +Release year: 2011 +ROM package: DIP-8 +ROM protocol: SPI +ROM socketed: y +ROM IC: W25Q32BV +Flashrom support: y +Internal flashing: y diff --git a/src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/cmos.default b/src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/cmos.default new file mode 100644 index 0000000..e74cec9 --- /dev/null +++ b/src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/cmos.default @@ -0,0 +1,8 @@ +## SPDX-License-Identifier: GPL-2.0-only + +boot_option=Fallback +debug_level=Debug +power_on_after_fail=Disable +nmi=Enable +sata_mode=AHCI +gfx_uma_size=32M diff --git a/src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/cmos.layout b/src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/cmos.layout new file mode 100644 index 0000000..8c6a055 --- /dev/null +++ b/src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/cmos.layout @@ -0,0 +1,66 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 6 debug_level + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail + +421 1 e 9 sata_mode + +# coreboot config options: cpu + +# coreboot config options: northbridge +432 3 e 11 gfx_uma_size + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +9 0 AHCI +9 1 IDE +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M + +# ----------------------------------------------------------------- +checksums + +checksum 392 439 984 diff --git a/src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/data.vbt b/src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/data.vbt new file mode 100644 index 0000000..2e26785 --- /dev/null +++ b/src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/data.vbt Binary files differ diff --git a/src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/early_init.c b/src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/early_init.c new file mode 100644 index 0000000..8510b7f --- /dev/null +++ b/src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/early_init.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <device/pci_ops.h> +#include <southbridge/intel/bd82x6x/pch.h> + +void bootblock_mainboard_early_init(void) +{ + pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN + | MC_LPC_EN | KBC_LPC_EN | GAMEH_LPC_EN | GAMEL_LPC_EN); +} diff --git a/src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/gma-mainboard.ads b/src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/gma-mainboard.ads new file mode 100644 index 0000000..d281ae5 --- /dev/null +++ b/src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/gma-mainboard.ads @@ -0,0 +1,17 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, -- DVI + HDMI3, -- HDMI + Analog, -- VGA + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/gpio.c b/src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/gpio.c new file mode 100644 index 0000000..9103226 --- /dev/null +++ b/src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/gpio.c @@ -0,0 +1,181 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, /* DRAM_LED */ + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_OUTPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, /* DRAM_LED */ + .gpio29 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_LOW, + .gpio12 = GPIO_LEVEL_LOW, + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, /* DRAM_LED */ + .gpio31 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio6 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_NATIVE, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_GPIO, /* GPU_BOOST slider switch */ + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, /* GPU_BOOST slider switch */ + .gpio49 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio57 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/hda_verb.c b/src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/hda_verb.c new file mode 100644 index 0000000..993767b --- /dev/null +++ b/src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/hda_verb.c @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0892, /* Codec Vendor / Device ID: Realtek */ + 0x1043848d, /* Subsystem ID */ + 15, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x1043848d), + AZALIA_PIN_CFG(0, 0x11, 0x99430140), + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x18, 0x01a19850), + AZALIA_PIN_CFG(0, 0x19, 0x02a19c60), + AZALIA_PIN_CFG(0, 0x1a, 0x0181305f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214c20), + AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1d, 0x4004c601), + AZALIA_PIN_CFG(0, 0x1e, 0x01452130), + AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)), + + 0x80862805, /* Codec Vendor / Device ID: Intel */ + 0x80862805, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(3, 0x80862805), + AZALIA_PIN_CFG(3, 0x05, 0x58560010), + AZALIA_PIN_CFG(3, 0x06, 0x58560020), + AZALIA_PIN_CFG(3, 0x07, 0x18560030), + +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/overridetree.cb b/src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/overridetree.cb new file mode 100644 index 0000000..ef24784 --- /dev/null +++ b/src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/overridetree.cb @@ -0,0 +1,97 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +chip northbridge/intel/sandybridge + register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}" + device domain 0 on + subsystemid 0x1043 0x844d inherit + + device ref peg10 on + smbios_slot_desc "SlotTypePciExpressGen2X16" "SlotLengthLong" "PCIEX16" "SlotDataBusWidth16X" + end + device ref igd on + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + end + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "pcie_port_coalesce" = "1" + register "usb_port_config" = "{ + {1, 0xb57, 0}, /* USB3_12 (rear USB 3.0 ports) */ + {1, 0xb57, 0}, /* USB3_12 (rear USB 3.0 ports) */ + {1, 0xb57, 1}, /* USB12 (rear USB2 above eSATA, red) */ + {1, 0xb57, 1}, /* USB12 (rear USB2 above eSATA, red) */ + {1, 0x57, 2}, /* USB34 (rear USB2 under PS/2, black) */ + {1, 0x57, 2}, /* USB34 (rear USB2 under PS/2, black) */ + {1, 0xb57, 3}, /* USB3_34 header (front panel USB 3.0) */ + {1, 0xb57, 3}, /* USB3_34 header (front panel USB 3.0) */ + {1, 0x357, 4}, /* USB56 header (front panel USB 2.0) */ + {1, 0x357, 4}, /* USB56 header (front panel USB 2.0) */ + {0, 0xb57, 5}, /* unconnected */ + {0, 0x343, 5}, /* unconnected */ + {1, 0xb57, 6}, /* integrated Bluetooth */ + {0, 0xb57, 6}, /* unconnected */ + }" + device ref hda on # Realtek ALC892 + subsystemid 0x1043 0x848d + end + device ref pcie_rp5 on + smbios_slot_desc "SlotTypePciExpressMini52pinWithoutBSKO" "SlotLengthShort" "WLAN" + end + device ref pcie_rp6 on end # uPD720200 for front panel USB3 + device ref pcie_rp7 on # RTL8111E GbE NIC + chip drivers/net + register "customized_leds" = "0x0c40" + device pci 00.0 on end + end + end + device ref pcie_rp8 on end # uPD720200 for rear USB3 ports + device ref lpc on + register "gen1_dec" = "0x00fc0295" + register "gen2_dec" = "0x00fc0a01" + chip superio/nuvoton/nct6776 + device pnp 2e.0 off end + device pnp 2e.1 off end + device pnp 2e.2 off end # COM1 + device pnp 2e.3 off end # COM2, IR + device pnp 2e.5 on # KBC + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 0x01 + irq 0x72 = 0x0c + irq 0xf0 = 0x83 + end + device pnp 2e.6 off end + device pnp 2e.7 off end + device pnp 2e.8 off end + device pnp 2e.9 on # GPIO2-5 + irq 0x30 = 0x0e + irq 0xe0 = 0xef + irq 0xe1 = 0x10 + irq 0xe4 = 0xf7 + end + device pnp 2e.a on # ACPI + irq 0xe4 = 0x10 + irq 0xe7 = 0x01 + end + device pnp 2e.b on # HWM, front panel LED + irq 0x30 = 0x01 + io 0x60 = 0x290 + end + device pnp 2e.d off end + device pnp 2e.e off end + device pnp 2e.f on # GPIO push-pull/open drain + irq 0xf0 = 0x9d + end + device pnp 2e.14 off end + device pnp 2e.16 on end # Deep sleep + device pnp 2e.17 on # GPIOA + irq 0xe0 = 0xff + end + end + end + device ref sata1 on + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x1f" # 0-3: internal SATA, 4: eSATA + end + end + end +end
-
Matt DeVillier (Code Review)