[M] Change in coreboot[main]: soc/intel/xeon_sp/gnr: Add soc_pci_domain_fill_ssdt

[Shuo Liu (Code Review)]

Attention is currently required from: Arthur Heymans, Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu.

Hello Arthur Heymans, Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/81374?usp=email

to look at the new patch set (#23).

The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)

Change subject: soc/intel/xeon_sp/gnr: Add soc_pci_domain_fill_ssdt
......................................................................

soc/intel/xeon_sp/gnr: Add soc_pci_domain_fill_ssdt

Domain device objects are created with HID/CID/UID/_OSC/_PXM

Dynamic domain SSDT generation could benefit the support of SoCs with
multiple SKUs, or the case where one set of codes supports multiple
SoCs. One possible side-effect might be the extra performance cost for
generating these tables, which should not bring big impact on high
performance server CPUs.

GNR codes run with dynamic domain SSDT generation to fit for both
GraniteRapids and SierraForest SoCs.

TEST=Build on intel/avenuecity CRB
TEST=Build on intel/beechnutcity CRB

Change-Id: I28bfdf74d8044235f79f67d832860d8b4306670c
Signed-off-by: Shuo Liu 
Signed-off-by: Jincheng Li 
---
M src/mainboard/intel/avenuecity_crb/dsdt.asl
M src/mainboard/intel/beechnutcity_crb/dsdt.asl
M src/soc/intel/xeon_sp/chip_gen6.c
A src/soc/intel/xeon_sp/gnr/acpi/uncore.asl
M src/soc/intel/xeon_sp/gnr/soc_acpi.c
M src/soc/intel/xeon_sp/include/soc/chip_common.h
6 files changed, 72 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/81374/23