Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63391 )
Change subject: sb/intel/common/early_{spi/smbus}: Don't use __SIMPLE_DEVICE__ ......................................................................
sb/intel/common/early_{spi/smbus}: Don't use __SIMPLE_DEVICE__
Change-Id: I93094dd56c0b97c9ddf5476cb723cddf0accb303 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/southbridge/intel/common/early_smbus.c M src/southbridge/intel/common/early_smbus.h M src/southbridge/intel/common/early_spi.h 3 files changed, 7 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/63391/1
diff --git a/src/southbridge/intel/common/early_smbus.c b/src/southbridge/intel/common/early_smbus.c index 6078b5f..8535857 100644 --- a/src/southbridge/intel/common/early_smbus.c +++ b/src/southbridge/intel/common/early_smbus.c @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
+#undef __SIMPLE_DEVICE__ + #include <device/pci_def.h> #include <device/pci_ids.h> #include <device/pci_ops.h> @@ -14,7 +16,7 @@ int smbus_enable_iobar(uintptr_t base) { /* Set the SMBus device statically. */ - const pci_devfn_t dev = PCI_DEV_SMBUS; + const struct device *dev = PCI_DEV_SMBUS;
/* Check to make sure we've got the right device. */ if (pci_read_config16(dev, PCI_VENDOR_ID) != PCI_VID_INTEL) diff --git a/src/southbridge/intel/common/early_smbus.h b/src/southbridge/intel/common/early_smbus.h index d6a7cbb..bf3b4ba 100644 --- a/src/southbridge/intel/common/early_smbus.h +++ b/src/southbridge/intel/common/early_smbus.h @@ -5,7 +5,7 @@
#include <device/pci_def.h>
-#define PCI_DEV_SMBUS PCI_DEV(0, 0x1f, 3) +#define PCI_DEV_SMBUS __pci_0_1f_3
#define SMB_BASE PCI_BASE_ADDRESS_4 #define HOSTC 0x40 diff --git a/src/southbridge/intel/common/early_spi.h b/src/southbridge/intel/common/early_spi.h index ae84f74..dc26f42 100644 --- a/src/southbridge/intel/common/early_spi.h +++ b/src/southbridge/intel/common/early_spi.h @@ -3,11 +3,13 @@ #ifndef SOUTHBRIDGE_INTEL_COMMON_EARLY_SPI_H #define SOUTHBRIDGE_INTEL_COMMON_EARLY_SPI_H
+#undef __SIMPLE_DEVICE__ + #include <device/pci_ops.h>
static inline void enable_spi_prefetching_and_caching(void) { - pci_update_config8(PCI_DEV(0, 0x1f, 0), 0xdc, ~(3 << 2), 2 << 2); + pci_update_config8(__pci_0_1f_0, 0xdc, ~(3 << 2), 2 << 2); }
#endif