Change in coreboot[master]: mb/intel/adlrvp: Add support for external clock buffer

[Subrata Banik (Code Review)]

Attention is currently required from: V Sowmya, Subrata Banik, Maulik V Vaghela, Angel Pons, Tim Wawrzynczak.
Hello V Sowmya, build bot (Jenkins), Maulik V Vaghela, Angel Pons, Tim Wawrzynczak, EricR Lai,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/59976

to look at the new patch set (#8).

Change subject: mb/intel/adlrvp: Add support for external clock buffer
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mb/intel/adlrvp: Add support for external clock buffer

ADL-P silicon can support 7 SRC CLK's and 10 CLKREQ signals.
Out of 7 SRCCLK's 3 will be used for CPU. Rests CLK SRC's are for PCH.
Now if more than 4 PCH devices connected on the platform, external
differential buffer chip needs to be placed at platform level.

A mainboard designer can choose to add an external clock chip,
and select the SRC CLK using CONFIG_CLKSRC_FOR_EXTERNAL_BUFFER.

CONFIG_CLKSRC_FOR_EXTERNAL_BUFFER provides the CLKSRC that feed clock
to discrete buffer for further distribution to platform.

TEST=Able to detect SD card connected at x4 PCIe Gen 3 Slot.

localhost ~ # dmesg | grep mmc
[    4.997840] mmc0: SDHCI controller on PCI [0000:ae:00.0] using ADMA
[    5.460902] mmc0: new ultra high speed DDR50 SDHC card at address aaaa
[    5.473555] mmcblk0: mmc0:aaaa SS08G 7.40 GiB
[    5.494268]  mmcblk0: p1
[    5.496967] audit: type=1400 audit(1638945356.685:2): avc:  denied  { search } for  pid=88 comm="kworker/0:3" name="mmc0:aaaa" dev="debugfs" ino=18919 scontext=u:r:kernel:s0 tcontext=u:object_r:debugfs_mmc:s0 tclass=dir permissive=1

Change-Id: I21f1155374049c90aa45db25d4128b39aa5898bb
Signed-off-by: Subrata Banik 
---
M src/mainboard/intel/adlrvp/Kconfig
M src/mainboard/intel/adlrvp/romstage_fsp_params.c
2 files changed, 39 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/59976/8