Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/27911
Change subject: src/northbridge: Fix typo ......................................................................
src/northbridge: Fix typo
Change-Id: I00094028036f33892362b935899e1bceef1da625 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/amd/amdfam10/amdfam10.h M src/northbridge/amd/amdfam10/resourcemap.c M src/northbridge/amd/amdht/h3ffeat.h M src/northbridge/amd/amdht/h3ncmn.c M src/northbridge/amd/amdmct/mct_ddr3/s3utils.c M src/northbridge/amd/amdmct/wrappers/mcti_d.c M src/northbridge/intel/gm45/ram_calc.c M src/northbridge/intel/i945/ram_calc.c M src/northbridge/intel/pineview/ram_calc.c M src/northbridge/intel/x4x/ram_calc.c 10 files changed, 14 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/27911/1
diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h index b744e96..5102b0b 100644 --- a/src/northbridge/amd/amdfam10/amdfam10.h +++ b/src/northbridge/amd/amdfam10/amdfam10.h @@ -314,7 +314,7 @@
// for 0x98 index and 0x9c data for DCT0 // for 0x198 index and 0x19c data for DCT1 -// even at ganged mode, 0x198/0x19c will be used for channnel B +// even at ganged mode, 0x198/0x19c will be used for channel B
#define DRAM_CTRL_ADDI_DATA_OFFSET 0x98 #define DCAO_DctOffset_SHIFT 0 @@ -368,9 +368,9 @@ #define DODCC_ProcOdt_75_OHMS 2
/* - for DDR2 400, 533, 667, F2x[1,0]9C_x[02:01], [03], [06:05], [07] controll timing of all DIMMs - for DDR2 800, DDR3 800, 1067, 1333, 1600, F2x[1,0]9C_x[02:01], [03], [06:05], [07] controll timing of DIMM0 - F2x[1,0]9C_x[102:101], [103], [106:105], [107] controll timing of DIMM1 + for DDR2 400, 533, 667, F2x[1,0]9C_x[02:01], [03], [06:05], [07] control timing of all DIMMs + for DDR2 800, DDR3 800, 1067, 1333, 1600, F2x[1,0]9C_x[02:01], [03], [06:05], [07] control timing of DIMM0 + F2x[1,0]9C_x[102:101], [103], [106:105], [107] control timing of DIMM1 So Socket F with Four Logical DIMM will only support DDR2 800 ? */ /* there are index +100 ===> for DIMM1 diff --git a/src/northbridge/amd/amdfam10/resourcemap.c b/src/northbridge/amd/amdfam10/resourcemap.c index 5db6886..362872b 100644 --- a/src/northbridge/amd/amdfam10/resourcemap.c +++ b/src/northbridge/amd/amdfam10/resourcemap.c @@ -121,7 +121,7 @@ * 0 = CPU writes may be posted * 1 = CPU writes must be non-posted * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp adddress bits of a 40-bit + * This field defines the upp address bits of a 40-bit * address that defines the end of a memory-mapped * I/O region n */ diff --git a/src/northbridge/amd/amdht/h3ffeat.h b/src/northbridge/amd/amdht/h3ffeat.h index 59e8feb..2cf4bd1 100644 --- a/src/northbridge/amd/amdht/h3ffeat.h +++ b/src/northbridge/amd/amdht/h3ffeat.h @@ -157,7 +157,7 @@ */ sPortDescriptor PortList[MAX_PLATFORM_LINKS*2];
- /* The number of coherent links comming off of each node (i.e. the 'Degree' of the node) */ + /* The number of coherent links coming off of each node (i.e. the 'Degree' of the node) */ u8 sysDegree[MAX_NODES]; /* The systems adjency (sysMatrix[i][j] is true if Node_i has a link to Node_j) */ BOOL sysMatrix[MAX_NODES][MAX_NODES]; @@ -169,7 +169,7 @@ u8 Perm[MAX_NODES]; /* The node mapping from the database to the system */ u8 ReversePerm[MAX_NODES]; /* The node mapping from the system to the database */
- /* Data for non-coherent initilization */ + /* Data for non-coherent initialization */ u8 AutoBusCurrent; u8 UsedCfgMapEntires;
diff --git a/src/northbridge/amd/amdht/h3ncmn.c b/src/northbridge/amd/amdht/h3ncmn.c index 5f656f5..6542ae4 100644 --- a/src/northbridge/amd/amdht/h3ncmn.c +++ b/src/northbridge/amd/amdht/h3ncmn.c @@ -1116,7 +1116,7 @@ * @param[in] *nb = this northbridge * @return = true - The link has the following status * LinkCon = 1, Link is connected - * InitComplete = 1,Link initilization is complete + * InitComplete = 1,Link initialization is complete * NC = 1, Link is coherent * UniP-cLDT = 0, Link is not Uniprocessor cLDT * LinkConPend = 0 Link connection is not pending diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c index 4c33a2f..388f064 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c @@ -846,7 +846,7 @@ dword &= (0x1 << 7); write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x94, dword);
- /* Restore DRAM Adddress/Timing Control Register */ + /* Restore DRAM Address/Timing Control Register */ write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x04, data->f2x9cx04); } else { /* Disable PHY auto-compensation engine */ diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c index 66730fc..3d9ff3e 100644 --- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c +++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c @@ -169,7 +169,7 @@ break; case NV_SPDCHK_RESTRT: val = 0; /* Exit current node initialization if any DIMM has SPD checksum error */ - //val = 1; /* Ignore faulty SPD checksum (DIMM will still be disabled), continue current node intialization */ + //val = 1; /* Ignore faulty SPD checksum (DIMM will still be disabled), continue current node initialization */ //val = 2; /* Override faulty SPD checksum (DIMM will be enabled), continue current node intialization */
if (get_option(&nvram, "dimm_spd_checksum") == CB_SUCCESS) diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c index 0e95341..5af3e16 100644 --- a/src/northbridge/intel/gm45/ram_calc.c +++ b/src/northbridge/intel/gm45/ram_calc.c @@ -107,7 +107,7 @@ }
/* Depending of UMA and TSEG configuration, TSEG might start at any - * 1 MiB aligment. As this may cause very greedy MTRR setup, push + * 1 MiB alignment. As this may cause very greedy MTRR setup, push * CBMEM top downwards to 4 MiB boundary. */ void *cbmem_top(void) diff --git a/src/northbridge/intel/i945/ram_calc.c b/src/northbridge/intel/i945/ram_calc.c index 15ba7f4..7ee7198 100644 --- a/src/northbridge/intel/i945/ram_calc.c +++ b/src/northbridge/intel/i945/ram_calc.c @@ -59,7 +59,7 @@ }
/* Depending of UMA and TSEG configuration, TSEG might start at any - * 1 MiB aligment. As this may cause very greedy MTRR setup, push + * 1 MiB alignment. As this may cause very greedy MTRR setup, push * CBMEM top downwards to 4 MiB boundary. */ void *cbmem_top(void) diff --git a/src/northbridge/intel/pineview/ram_calc.c b/src/northbridge/intel/pineview/ram_calc.c index d116709..62855c2 100644 --- a/src/northbridge/intel/pineview/ram_calc.c +++ b/src/northbridge/intel/pineview/ram_calc.c @@ -95,7 +95,7 @@ }
/* Depending of UMA and TSEG configuration, TSEG might start at any - * 1 MiB aligment. As this may cause very greedy MTRR setup, push + * 1 MiB alignment. As this may cause very greedy MTRR setup, push * CBMEM top downwards to 4 MiB boundary. */ void *cbmem_top(void) diff --git a/src/northbridge/intel/x4x/ram_calc.c b/src/northbridge/intel/x4x/ram_calc.c index 49afdc3..1f1c13f 100644 --- a/src/northbridge/intel/x4x/ram_calc.c +++ b/src/northbridge/intel/x4x/ram_calc.c @@ -93,7 +93,7 @@ }
/* Depending of UMA and TSEG configuration, TSEG might start at any - * 1 MiB aligment. As this may cause very greedy MTRR setup, push + * 1 MiB alignment. As this may cause very greedy MTRR setup, push * CBMEM top downwards to 4 MiB boundary. */ void *cbmem_top(void)
-
Elyes HAOUAS (Code Review)