Change in coreboot[master]: mb/intel/adlrvp_m: Enable LTR for PCIE - coreboot-gerrit

19 May 2021


      Attention is currently required from: Bora Guvendik, Ryan Albazzaz, Bernardo Perez Priego.
Ryan A Albazzaz has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54492 )
Change subject: mb/intel/adlrvp_m: Enable LTR for PCIE
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Patch Set 1: Code-Review+1
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: If65d08a46b9e7304fbe4b92b7f1e6d4e08c599e7
Gerrit-Change-Number: 54492
Gerrit-PatchSet: 1
Gerrit-Owner: Bernardo Perez Priego bernardo.perez.priego@intel.com
Gerrit-Reviewer: Bora Guvendik bora.guvendik@intel.com
Gerrit-Reviewer: Ryan A Albazzaz ryan.a.albazzaz@intel.corp-partner.google.com
Gerrit-Reviewer: Ryan Albazzaz ryan.a.albazzaz@intel.com
Gerrit-Reviewer: Selma Bensaid selma.bensaid@intel.com
Gerrit-Attention: Bora Guvendik bora.guvendik@intel.com
Gerrit-Attention: Ryan Albazzaz ryan.a.albazzaz@intel.com
Gerrit-Attention: Bernardo Perez Priego bernardo.perez.priego@intel.com
Gerrit-Comment-Date: Tue, 18 May 2021 16:25:54 +0000
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