Change in coreboot[master]: soc/intel/common/dmi: Move DMI defines into DMI driver header
Srinidhi N Kaushik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48257 )
Change subject: soc/intel/common/dmi: Move DMI defines into DMI driver header ......................................................................
soc/intel/common/dmi: Move DMI defines into DMI driver header
Move definitions of DMI control register and Secure Register Lock (SRL) bit into common/block/dmi driver header file.
BUG=b:171534504
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: Iefee818f58f399d4a127662a300b6e132494bad0 --- M src/soc/intel/common/block/include/intelblocks/dmi.h M src/soc/intel/tigerlake/bootblock/pch.c 2 files changed, 4 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/48257/1
diff --git a/src/soc/intel/common/block/include/intelblocks/dmi.h b/src/soc/intel/common/block/include/intelblocks/dmi.h index b771b22..55bf20d 100644 --- a/src/soc/intel/common/block/include/intelblocks/dmi.h +++ b/src/soc/intel/common/block/include/intelblocks/dmi.h @@ -5,6 +5,9 @@
#include <types.h>
+#define PCR_DMI_DMICTL 0x2234 +#define PCR_DMI_DMICTL_SRLOCK (1 << 31) + /* * Takes base, size and destination ID and configures the GPMR * for accessing the region. diff --git a/src/soc/intel/tigerlake/bootblock/pch.c b/src/soc/intel/tigerlake/bootblock/pch.c index 5c4d1d5..5a63b40 100644 --- a/src/soc/intel/tigerlake/bootblock/pch.c +++ b/src/soc/intel/tigerlake/bootblock/pch.c @@ -11,6 +11,7 @@ #include <device/mmio.h> #include <device/device.h> #include <device/pci_ops.h> +#include <intelblocks/dmi.h> #include <intelblocks/fast_spi.h> #include <intelblocks/gspi.h> #include <intelblocks/lpc_lib.h> @@ -36,9 +37,6 @@ #define PCR_PSFX_TO_SHDW_PCIEN_IOEN 0x01 #define PCR_PSFX_T0_SHDW_PCIEN 0x1C
-#define PCR_DMI_DMICTL 0x2234 -#define PCR_DMI_DMICTL_SRLOCK (1 << 31) - #define PCR_DMI_ACPIBA 0x27B4 #define PCR_DMI_ACPIBDID 0x27B8 #define PCR_DMI_PMBASEA 0x27AC
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48257 )
Change subject: soc/intel/common/dmi: Move DMI defines into DMI driver header ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/48257/1/src/soc/intel/tigerlake/boo... File src/soc/intel/tigerlake/bootblock/pch.c:
https://review.coreboot.org/c/coreboot/+/48257/1/src/soc/intel/tigerlake/boo... PS1, Line 39: #define PCR_DMI_DMICTL 0x2234 : #define PCR_DMI_DMICTL_SRLOCK (1 << 31) This will have to be removed from pch.c for all Intel SoCs.
https://review.coreboot.org/c/coreboot/+/48257/1/src/soc/intel/tigerlake/boo... PS1, Line 105: pch_check_decode_enable Maybe in a follow-up change, but I think we should add a helper for this as well since it seems to be used by all SoCs.
dmi_check_srlock()
Hello build bot (Jenkins), Furquan Shaikh, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48257
to look at the new patch set (#2).
Change subject: soc/intel/common/dmi: Move DMI defines into DMI driver header ......................................................................
soc/intel/common/dmi: Move DMI defines into DMI driver header
Move definitions of DMI control register and Secure Register Lock (SRL) bit into common/block/dmi driver header file.
BUG=b:171534504
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: Iefee818f58f399d4a127662a300b6e132494bad0 --- M src/soc/intel/alderlake/bootblock/pch.c M src/soc/intel/cannonlake/bootblock/pch.c M src/soc/intel/common/block/include/intelblocks/dmi.h M src/soc/intel/elkhartlake/bootblock/pch.c M src/soc/intel/icelake/bootblock/pch.c M src/soc/intel/jasperlake/bootblock/pch.c M src/soc/intel/skylake/bootblock/pch.c M src/soc/intel/tigerlake/bootblock/pch.c M src/soc/intel/xeon_sp/pch.c 9 files changed, 11 insertions(+), 22 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/48257/2
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48257 )
Change subject: soc/intel/common/dmi: Move DMI defines into DMI driver header ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/48257/1/src/soc/intel/tigerlake/boo... File src/soc/intel/tigerlake/bootblock/pch.c:
https://review.coreboot.org/c/coreboot/+/48257/1/src/soc/intel/tigerlake/boo... PS1, Line 39: #define PCR_DMI_DMICTL 0x2234 : #define PCR_DMI_DMICTL_SRLOCK (1 << 31)
This will have to be removed from pch.c for all Intel SoCs.
Done
https://review.coreboot.org/c/coreboot/+/48257/1/src/soc/intel/tigerlake/boo... PS1, Line 105: pch_check_decode_enable
Maybe in a follow-up change, but I think we should add a helper for this as well since it seems to b […]
Sure
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48257 )
Change subject: soc/intel/common/dmi: Move DMI defines into DMI driver header ......................................................................
Patch Set 2: Code-Review+2
Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48257 )
Change subject: soc/intel/common/dmi: Move DMI defines into DMI driver header ......................................................................
Patch Set 2: Code-Review+2
Furquan Shaikh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48257 )
Change subject: soc/intel/common/dmi: Move DMI defines into DMI driver header ......................................................................
soc/intel/common/dmi: Move DMI defines into DMI driver header
Move definitions of DMI control register and Secure Register Lock (SRL) bit into common/block/dmi driver header file.
BUG=b:171534504
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: Iefee818f58f399d4a127662a300b6e132494bad0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48257 Reviewed-by: Furquan Shaikh furquan@google.com Reviewed-by: Duncan Laurie dlaurie@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/alderlake/bootblock/pch.c M src/soc/intel/cannonlake/bootblock/pch.c M src/soc/intel/common/block/include/intelblocks/dmi.h M src/soc/intel/elkhartlake/bootblock/pch.c M src/soc/intel/icelake/bootblock/pch.c M src/soc/intel/jasperlake/bootblock/pch.c M src/soc/intel/skylake/bootblock/pch.c M src/soc/intel/tigerlake/bootblock/pch.c M src/soc/intel/xeon_sp/pch.c 9 files changed, 11 insertions(+), 22 deletions(-)
Approvals: build bot (Jenkins): Verified Duncan Laurie: Looks good to me, approved Furquan Shaikh: Looks good to me, approved
diff --git a/src/soc/intel/alderlake/bootblock/pch.c b/src/soc/intel/alderlake/bootblock/pch.c index bc921e3..528e4de 100644 --- a/src/soc/intel/alderlake/bootblock/pch.c +++ b/src/soc/intel/alderlake/bootblock/pch.c @@ -9,6 +9,7 @@ #include <device/mmio.h> #include <device/device.h> #include <device/pci_ops.h> +#include <intelblocks/dmi.h> #include <intelblocks/fast_spi.h> #include <intelblocks/gspi.h> #include <intelblocks/lpc_lib.h> @@ -34,9 +35,6 @@ #define PCR_PSFX_TO_SHDW_PCIEN_IOEN 0x01 #define PCR_PSFX_T0_SHDW_PCIEN 0x1C
-#define PCR_DMI_DMICTL 0x2234 -#define PCR_DMI_DMICTL_SRLOCK (1 << 31) - #define PCR_DMI_ACPIBA 0x27B4 #define PCR_DMI_ACPIBDID 0x27B8 #define PCR_DMI_PMBASEA 0x27AC diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c index 8ebfb3d..a05e565 100644 --- a/src/soc/intel/cannonlake/bootblock/pch.c +++ b/src/soc/intel/cannonlake/bootblock/pch.c @@ -4,6 +4,7 @@ #include <device/mmio.h> #include <device/device.h> #include <device/pci_ops.h> +#include <intelblocks/dmi.h> #include <intelblocks/fast_spi.h> #include <intelblocks/gspi.h> #include <intelblocks/lpc_lib.h> @@ -32,9 +33,6 @@ #define PCR_PSFX_TO_SHDW_PCIEN_IOEN 0x01 #define PCR_PSFX_T0_SHDW_PCIEN 0x1C
-#define PCR_DMI_DMICTL 0x2234 -#define PCR_DMI_DMICTL_SRLOCK (1 << 31) - #define PCR_DMI_ACPIBA 0x27B4 #define PCR_DMI_ACPIBDID 0x27B8 #define PCR_DMI_PMBASEA 0x27AC diff --git a/src/soc/intel/common/block/include/intelblocks/dmi.h b/src/soc/intel/common/block/include/intelblocks/dmi.h index b771b22..55bf20d 100644 --- a/src/soc/intel/common/block/include/intelblocks/dmi.h +++ b/src/soc/intel/common/block/include/intelblocks/dmi.h @@ -5,6 +5,9 @@
#include <types.h>
+#define PCR_DMI_DMICTL 0x2234 +#define PCR_DMI_DMICTL_SRLOCK (1 << 31) + /* * Takes base, size and destination ID and configures the GPMR * for accessing the region. diff --git a/src/soc/intel/elkhartlake/bootblock/pch.c b/src/soc/intel/elkhartlake/bootblock/pch.c index e1b7d85..e1414f1 100644 --- a/src/soc/intel/elkhartlake/bootblock/pch.c +++ b/src/soc/intel/elkhartlake/bootblock/pch.c @@ -5,6 +5,7 @@ #include <device/device.h> #include <device/mmio.h> #include <device/pci_ops.h> +#include <intelblocks/dmi.h> #include <intelblocks/fast_spi.h> #include <intelblocks/gspi.h> #include <intelblocks/lpc_lib.h> @@ -31,9 +32,6 @@ #define PCR_PSFX_TO_SHDW_PCIEN_IOEN 0x01 #define PCR_PSFX_T0_SHDW_PCIEN 0x1C
-#define PCR_DMI_DMICTL 0x2234 -#define PCR_DMI_DMICTL_SRLOCK (1 << 31) - #define PCR_DMI_ACPIBA 0x27B4 #define PCR_DMI_ACPIBDID 0x27B8 #define PCR_DMI_PMBASEA 0x27AC diff --git a/src/soc/intel/icelake/bootblock/pch.c b/src/soc/intel/icelake/bootblock/pch.c index a6b6b20..08edfee 100644 --- a/src/soc/intel/icelake/bootblock/pch.c +++ b/src/soc/intel/icelake/bootblock/pch.c @@ -3,6 +3,7 @@ #include <device/mmio.h> #include <device/device.h> #include <device/pci_ops.h> +#include <intelblocks/dmi.h> #include <intelblocks/fast_spi.h> #include <intelblocks/gspi.h> #include <intelblocks/lpc_lib.h> @@ -27,9 +28,6 @@ #define PCR_PSFX_TO_SHDW_PCIEN_IOEN 0x01 #define PCR_PSFX_T0_SHDW_PCIEN 0x1C
-#define PCR_DMI_DMICTL 0x2234 -#define PCR_DMI_DMICTL_SRLOCK (1 << 31) - #define PCR_DMI_ACPIBA 0x27B4 #define PCR_DMI_ACPIBDID 0x27B8 #define PCR_DMI_PMBASEA 0x27AC diff --git a/src/soc/intel/jasperlake/bootblock/pch.c b/src/soc/intel/jasperlake/bootblock/pch.c index 96a7dc2..d98d5a8 100644 --- a/src/soc/intel/jasperlake/bootblock/pch.c +++ b/src/soc/intel/jasperlake/bootblock/pch.c @@ -5,6 +5,7 @@ #include <device/mmio.h> #include <device/device.h> #include <device/pci_ops.h> +#include <intelblocks/dmi.h> #include <intelblocks/fast_spi.h> #include <intelblocks/gspi.h> #include <intelblocks/lpc_lib.h> @@ -31,9 +32,6 @@ #define PCR_PSFX_TO_SHDW_PCIEN_IOEN 0x01 #define PCR_PSFX_T0_SHDW_PCIEN 0x1C
-#define PCR_DMI_DMICTL 0x2234 -#define PCR_DMI_DMICTL_SRLOCK (1 << 31) - #define PCR_DMI_ACPIBA 0x27B4 #define PCR_DMI_ACPIBDID 0x27B8 #define PCR_DMI_PMBASEA 0x27AC diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index 38ae916..a5bbb09 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -3,6 +3,7 @@ #include <device/device.h> #include <device/pci_def.h> #include <intelblocks/cse.h> +#include <intelblocks/dmi.h> #include <intelblocks/fast_spi.h> #include <intelblocks/itss.h> #include <intelblocks/lpc_lib.h> @@ -20,8 +21,6 @@ #include <soc/pmc.h> #include "../chip.h"
-#define PCR_DMI_DMICTL 0x2234 -#define PCR_DMI_DMICTL_SRLOCK (1 << 31) #define PCR_DMI_ACPIBA 0x27B4 #define PCR_DMI_ACPIBDID 0x27B8 #define PCR_DMI_PMBASEA 0x27AC diff --git a/src/soc/intel/tigerlake/bootblock/pch.c b/src/soc/intel/tigerlake/bootblock/pch.c index 5c4d1d5..5a63b40 100644 --- a/src/soc/intel/tigerlake/bootblock/pch.c +++ b/src/soc/intel/tigerlake/bootblock/pch.c @@ -11,6 +11,7 @@ #include <device/mmio.h> #include <device/device.h> #include <device/pci_ops.h> +#include <intelblocks/dmi.h> #include <intelblocks/fast_spi.h> #include <intelblocks/gspi.h> #include <intelblocks/lpc_lib.h> @@ -36,9 +37,6 @@ #define PCR_PSFX_TO_SHDW_PCIEN_IOEN 0x01 #define PCR_PSFX_T0_SHDW_PCIEN 0x1C
-#define PCR_DMI_DMICTL 0x2234 -#define PCR_DMI_DMICTL_SRLOCK (1 << 31) - #define PCR_DMI_ACPIBA 0x27B4 #define PCR_DMI_ACPIBDID 0x27B8 #define PCR_DMI_PMBASEA 0x27AC diff --git a/src/soc/intel/xeon_sp/pch.c b/src/soc/intel/xeon_sp/pch.c index 8de7743..44824ca 100644 --- a/src/soc/intel/xeon_sp/pch.c +++ b/src/soc/intel/xeon_sp/pch.c @@ -3,6 +3,7 @@ #include <device/pci_ops.h> #include <soc/pci_devs.h> #include <soc/pcr_ids.h> +#include <intelblocks/dmi.h> #include <intelblocks/pcr.h> #include <intelblocks/rtc.h> #include <intelblocks/p2sb.h> @@ -11,8 +12,6 @@ #include <soc/pmc.h> #include <console/console.h>
-#define PCR_DMI_DMICTL 0x2234 -#define PCR_DMI_DMICTL_SRLOCK (1 << 31) #define PCR_DMI_ACPIBA 0x27B4 #define PCR_DMI_ACPIBDID 0x27B8 #define PCR_DMI_PMBASEA 0x27AC
-
Duncan Laurie (Code Review) -
Furquan Shaikh (Code Review)
-
Srinidhi N Kaushik (Code Review)