[M] Change in coreboot[master]: common/acpi/dptc: Implement DTTS Proposal

[LeilaCY Lin (Code Review)]

Attention is currently required from: Raul Rangel, EricKY Cheng, Matt DeVillier, Paul Menzel, Tim Van Patten, Eric Peers, Jason Glenesk, Caveh Jalali, Tim Wawrzynczak, Fred Reitberger, Karthikeyan Ramasubramanian, Boris Mittelberg, Felix Held.

LeilaCY Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68471 )

Change subject: common/acpi/dptc: Implement DTTS Proposal
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Patch Set 25:

(2 comments)

File src/soc/amd/common/acpi/dptc.asl:

https://review.coreboot.org/c/coreboot/+/68471/comment/957f9cd8_e742a349 
PS21, Line 47: 123
> > As I know it is 123K = 50C […]

There is an offset of temperature value stored in mapped memory. 
This allows reporting a temperature range of 200K to 454K = -73C to 181C.
[static void update_mapped_memory(void)](https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/plat...)
[#define EC_TEMP_SENSOR_OFFSET 200](https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/plat...)

So if the temperature is 50C, there will store 123(0x7b) in mapped memory.
50C=323K, 323-200(offset)=123(0x7b), example

https://review.coreboot.org/c/coreboot/+/68471/comment/3c212a1e_2c50b98c 
PS21, Line 56: 118
> Also incorrect. […]

Because there is an offset(200) of temperature value stored in mapped memory.
45C will store 118(0x76) in mapped memory.
45C=318K, 318-200(offset)=118(0x76)