Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25565 )
Change subject: src/cpu/intel: Add model_f6x ......................................................................
Patch Set 30:
(2 comments)
https://review.coreboot.org/#/c/25565/26/src/cpu/intel/model_f6x/model_f6x_i... File src/cpu/intel/model_f6x/model_f6x_init.c:
https://review.coreboot.org/#/c/25565/26/src/cpu/intel/model_f6x/model_f6x_i... PS26, Line 33: wrmsr(MSR_EBC_FREQUENCY_ID, msr_2c); Which datasheet did you get this from? The IA32 manual I was looking at described these MSR bits 31-24 as read-only, latched from bootstraps on hardware reset.
https://review.coreboot.org/#/c/25565/26/src/cpu/intel/model_f6x/model_f6x_i... PS26, Line 72:
here with printf , on debug console, CPU0 and CPU1 have the same MSR(0x2c).lo value = 0x11120511. […]
Ramstage pretty much shuts down CPU1 so this register might get reset when woken up again. I am not convinced of writing MSR 0x2c in the first place.
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Kyösti Mälkki (Code Review)