Roy Mingi Park has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31405
Change subject: soc/intel/cannonlake: Define VR settings ......................................................................
soc/intel/cannonlake: Define VR settings
Define VR settings configuration as per board design.
BUG=N/A TEST=Build and boot up into sarien platform.
Change-Id: Ic9927943b1f8fab687659fd1d6da0e3988a3aba2 Signed-off-by: Roy Mingi Park roy.mingi.park@intel.com --- M src/soc/intel/cannonlake/vr_config.c 1 file changed, 48 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/31405/1
diff --git a/src/soc/intel/cannonlake/vr_config.c b/src/soc/intel/cannonlake/vr_config.c index fff68c7..25270d8 100644 --- a/src/soc/intel/cannonlake/vr_config.c +++ b/src/soc/intel/cannonlake/vr_config.c @@ -19,7 +19,54 @@ #include <soc/vr_config.h>
static const struct vr_config default_configs[NUM_VR_DOMAINS] = { - /* TODO: define this*/ + [VR_SYSTEM_AGENT] = { + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(6), + .voltage_limit = 1520, + }, + [VR_IA_CORE] = { + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(70), + .voltage_limit = 1520, + }, + [VR_GT_UNSLICED] = { + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(31), + .voltage_limit = 1520, + }, + [VR_GT_SLICED] = { + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(31), + .voltage_limit = 1520, + }, };
void fill_vr_domain_config(void *params,
Roy Mingi Park has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31405 )
Change subject: soc/intel/cannonlake: Define VR settings ......................................................................
Patch Set 1: Code-Review+1
Hello Patrick Rudolph, Bora Guvendik, build bot (Jenkins), Lijian Zhao, Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31405
to look at the new patch set (#2).
Change subject: soc/intel/cannonlake: Define VR settings ......................................................................
soc/intel/cannonlake: Define VR settings
Define VR settings configuration as per board design.
BUG=N/A TEST=Build and boot up into sarien platform.
Change-Id: Ic9927943b1f8fab687659fd1d6da0e3988a3aba2 Signed-off-by: Roy Mingi Park roy.mingi.park@intel.com --- M src/soc/intel/cannonlake/include/soc/vr_config.h M src/soc/intel/cannonlake/vr_config.c 2 files changed, 50 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/31405/2
Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31405 )
Change subject: soc/intel/cannonlake: Define VR settings ......................................................................
Patch Set 2: Code-Review+1
Looks ok to me but someone from Intel should confirm the numbers..
Roy Mingi Park has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31405 )
Change subject: soc/intel/cannonlake: Define VR settings ......................................................................
Patch Set 2:
Patch Set 2: Code-Review+1
Looks ok to me but someone from Intel should confirm the numbers..
The numbers are directly referred from VRTT test results on both Sarien and Arcada.
Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31405 )
Change subject: soc/intel/cannonlake: Define VR settings ......................................................................
Patch Set 2: Code-Review+2
Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31405 )
Change subject: soc/intel/cannonlake: Define VR settings ......................................................................
soc/intel/cannonlake: Define VR settings
Define VR settings configuration as per board design.
BUG=N/A TEST=Build and boot up into sarien platform.
Change-Id: Ic9927943b1f8fab687659fd1d6da0e3988a3aba2 Signed-off-by: Roy Mingi Park roy.mingi.park@intel.com Reviewed-on: https://review.coreboot.org/c/31405 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Duncan Laurie dlaurie@chromium.org --- M src/soc/intel/cannonlake/include/soc/vr_config.h M src/soc/intel/cannonlake/vr_config.c 2 files changed, 50 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Duncan Laurie: Looks good to me, approved
diff --git a/src/soc/intel/cannonlake/include/soc/vr_config.h b/src/soc/intel/cannonlake/include/soc/vr_config.h index 385767d..8bcf001 100644 --- a/src/soc/intel/cannonlake/include/soc/vr_config.h +++ b/src/soc/intel/cannonlake/include/soc/vr_config.h @@ -55,6 +55,8 @@ uint16_t dc_loadline; };
+#define VR_CFG_AMP(i) ((i) * 4) + /* VrConfig Settings for 4 domains * 0 = System Agent, 1 = IA Core, * 2 = GT unsliced, 3 = GT sliced */ diff --git a/src/soc/intel/cannonlake/vr_config.c b/src/soc/intel/cannonlake/vr_config.c index fff68c7..25270d8 100644 --- a/src/soc/intel/cannonlake/vr_config.c +++ b/src/soc/intel/cannonlake/vr_config.c @@ -19,7 +19,54 @@ #include <soc/vr_config.h>
static const struct vr_config default_configs[NUM_VR_DOMAINS] = { - /* TODO: define this*/ + [VR_SYSTEM_AGENT] = { + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(6), + .voltage_limit = 1520, + }, + [VR_IA_CORE] = { + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(70), + .voltage_limit = 1520, + }, + [VR_GT_UNSLICED] = { + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(31), + .voltage_limit = 1520, + }, + [VR_GT_SLICED] = { + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(31), + .voltage_limit = 1520, + }, };
void fill_vr_domain_config(void *params,
-
Duncan Laurie (Code Review) -
Patrick Georgi (Code Review)
-
Roy Mingi Park (Code Review)