Change in coreboot[master]: soc/intel/xeon_sp/cpx: Implement hide/unhide P2SB traditional dance
Andrey Petrov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40921 )
Change subject: soc/intel/xeon_sp/cpx: Implement hide/unhide P2SB traditional dance ......................................................................
soc/intel/xeon_sp/cpx: Implement hide/unhide P2SB traditional dance
Perform the P2SB hide/unhide trick. This is needed so that BAR0 (0xfd000000) is not reclaimed by resource allocator, since it can not deal with a device that does not exist (hidden).
Signed-off-by: Andrey Petrov anpetrov@fb.com Change-Id: I5db0ae4e31d72ba86efba5728b2afc68d3180d5d --- M src/soc/intel/xeon_sp/cpx/chip.c 1 file changed, 3 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/40921/1
diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c index 196f3df..0a4cea6 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.c +++ b/src/soc/intel/xeon_sp/cpx/chip.c @@ -7,6 +7,7 @@ #include <cpu/x86/lapic.h> #include <device/pci.h> #include <fsp/api.h> +#include <intelblocks/p2sb.h> #include <soc/cpu.h> #include <soc/ramstage.h> #include <soc/pm.h> @@ -73,7 +74,7 @@
static void chip_final(void *data) { - /* nothing implemented yet */ + p2sb_hide(); }
static void chip_init(void *data) @@ -82,6 +83,7 @@ fsp_silicon_init(false); pch_enable_ioapic(NULL); setup_lapic(); + p2sb_unhide(); }
struct chip_operations soc_intel_xeon_sp_cpx_ops = {
Hello Anjaneya "Reddy" Chagam, Maxim Polyakov, Jonathan Zhang, David Hendricks, Rocky Phagura, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40921
to look at the new patch set (#2).
Change subject: soc/intel/xeon_sp/cpx: Implement hide/unhide P2SB traditional dance ......................................................................
soc/intel/xeon_sp/cpx: Implement hide/unhide P2SB traditional dance
Perform the P2SB hide/unhide trick. This is needed so that BAR0 (0xfd000000) is not reclaimed by resource allocator, since it can not deal with a device that does not exist (hidden).
Signed-off-by: Andrey Petrov anpetrov@fb.com Change-Id: I5db0ae4e31d72ba86efba5728b2afc68d3180d5d --- M src/soc/intel/xeon_sp/cpx/chip.c 1 file changed, 3 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/40921/2
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40921 )
Change subject: soc/intel/xeon_sp/cpx: Implement hide/unhide P2SB traditional dance ......................................................................
Patch Set 2: Code-Review+2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40921 )
Change subject: soc/intel/xeon_sp/cpx: Implement hide/unhide P2SB traditional dance ......................................................................
Patch Set 4: Code-Review+2
Ah yes, you need to perform these traditional dances so as to prevent the voodoo that Intel uses for newer chips from escaping out of the jail of cursed sand. I am pretty sure we will soon need to add a magic wand to coreboot.
Andrey Petrov has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40921 )
Change subject: soc/intel/xeon_sp/cpx: Implement hide/unhide P2SB traditional dance ......................................................................
soc/intel/xeon_sp/cpx: Implement hide/unhide P2SB traditional dance
Perform the P2SB hide/unhide trick. This is needed so that BAR0 (0xfd000000) is not reclaimed by resource allocator, since it can not deal with a device that does not exist (hidden).
Signed-off-by: Andrey Petrov anpetrov@fb.com Change-Id: I5db0ae4e31d72ba86efba5728b2afc68d3180d5d Reviewed-on: https://review.coreboot.org/c/coreboot/+/40921 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com Reviewed-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/soc/intel/xeon_sp/cpx/chip.c 1 file changed, 3 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Maxim Polyakov: Looks good to me, approved
diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c index 196f3df..0a4cea6 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.c +++ b/src/soc/intel/xeon_sp/cpx/chip.c @@ -7,6 +7,7 @@ #include <cpu/x86/lapic.h> #include <device/pci.h> #include <fsp/api.h> +#include <intelblocks/p2sb.h> #include <soc/cpu.h> #include <soc/ramstage.h> #include <soc/pm.h> @@ -73,7 +74,7 @@
static void chip_final(void *data) { - /* nothing implemented yet */ + p2sb_hide(); }
static void chip_init(void *data) @@ -82,6 +83,7 @@ fsp_silicon_init(false); pch_enable_ioapic(NULL); setup_lapic(); + p2sb_unhide(); }
struct chip_operations soc_intel_xeon_sp_cpx_ops = {
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40921 )
Change subject: soc/intel/xeon_sp/cpx: Implement hide/unhide P2SB traditional dance ......................................................................
Patch Set 5:
Automatic boot test returned (PASS/FAIL/TOTAL): 4/0/4 Emulation targets: "QEMU x86 q35/ich9" using payload TianoCore : SUCCESS : https://lava.9esec.io/r/3088 "QEMU x86 q35/ich9" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/3087 "QEMU x86 i440fx/piix4" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/3086 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/3085
Please note: This test is under development and might not be accurate at all!
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9elements QA (Code Review) -
Andrey Petrov (Code Review)
-
Angel Pons (Code Review)
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Maxim Polyakov (Code Review)