Change in coreboot[master]: soc/intel/xeon_sp/cpx: code change for FSP ww24 release

[Jonathan Zhang (Code Review)]

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42334 )

Change subject: soc/intel/xeon_sp/cpx: code change for FSP ww24 release
......................................................................

soc/intel/xeon_sp/cpx: code change for FSP ww24 release

With CPX-SP FSP ww24 release:
* There are changes in PLATFORM_DATA structure, so hob_display.c
is updated.
* There are changes in UPD parameters, so romstage.c is updated.

Signed-off-by: Jonathan Zhang 
Change-Id: I39cef8aa4a02ce313f0fd75aa6b2ea6668ac687b
---
M src/soc/intel/xeon_sp/cpx/hob_display.c
M src/soc/intel/xeon_sp/cpx/romstage.c
2 files changed, 8 insertions(+), 12 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/42334/1

diff --git a/src/soc/intel/xeon_sp/cpx/hob_display.c b/src/soc/intel/xeon_sp/cpx/hob_display.c
index 37c0c7e..d10a0f6 100644
--- a/src/soc/intel/xeon_sp/cpx/hob_display.c
+++ b/src/soc/intel/xeon_sp/cpx/hob_display.c
@@ -97,14 +97,14 @@
    printk(BIOS_DEBUG, "\t===================== PLATFORM DATA =====================\n");
    printk(BIOS_DEBUG, "\tPlatGlobalIoBase: 0x%x\n", hob->PlatformData.PlatGlobalIoBase);
    printk(BIOS_DEBUG, "\tPlatGlobalIoLimit: 0x%x\n", hob->PlatformData.PlatGlobalIoLimit);
-	printk(BIOS_DEBUG, "\tPlatGlobalMmiolBase: 0x%x\n",
-		hob->PlatformData.PlatGlobalMmiolBase);
-	printk(BIOS_DEBUG, "\tPlatGlobalMmiolLimit: 0x%x\n",
-		hob->PlatformData.PlatGlobalMmiolLimit);
-	printk(BIOS_DEBUG, "\tPlatGlobalMmiohBase: 0x%llx\n",
-		hob->PlatformData.PlatGlobalMmiohBase);
-	printk(BIOS_DEBUG, "\tPlatGlobalMmiohLimit: 0x%llx\n",
-		hob->PlatformData.PlatGlobalMmiohLimit);
+	printk(BIOS_DEBUG, "\tPlatGlobalMmio32Base: 0x%x\n",
+		hob->PlatformData.PlatGlobalMmio32Base);
+	printk(BIOS_DEBUG, "\tPlatGlobalMmio32Limit: 0x%x\n",
+		hob->PlatformData.PlatGlobalMmio32Limit);
+	printk(BIOS_DEBUG, "\tPlatGlobalMmio64Base: 0x%llx\n",
+		hob->PlatformData.PlatGlobalMmio64Base);
+	printk(BIOS_DEBUG, "\tPlatGlobalMmio64Limit: 0x%llx\n",
+		hob->PlatformData.PlatGlobalMmio64Limit);
    printk(BIOS_DEBUG, "\tMemTsegSize: 0x%x\n", hob->PlatformData.MemTsegSize);
    printk(BIOS_DEBUG, "\tMemIedSize: 0x%x\n", hob->PlatformData.MemIedSize);
    printk(BIOS_DEBUG, "\tPciExpressBase: 0x%llx\n", hob->PlatformData.PciExpressBase);
diff --git a/src/soc/intel/xeon_sp/cpx/romstage.c b/src/soc/intel/xeon_sp/cpx/romstage.c
index cbaa006..4b97ddc 100644
--- a/src/soc/intel/xeon_sp/cpx/romstage.c
+++ b/src/soc/intel/xeon_sp/cpx/romstage.c
@@ -33,7 +33,6 @@
    /* Bitmask for valid sockets supported by the board */
    m_cfg->BoardTypeBitmask = 0x11111111;

-	m_cfg->mmiolSize = 0x0;
    m_cfg->mmiohBase = 0x2000;

/* default: 0x1 (enable), set to 0x2 (auto) */
@@ -65,9 +64,6 @@
    /* the wait time in units of 1000us for PBSP to check in */
    m_cfg->WaitTimeForPSBP = 0x7530;

-	m_cfg->OemHookPostTopologyDiscovery = 0xFFF7727B;
-	m_cfg->OemGetResourceMapUpdate = 0xFFF7727C;
-
    /* Needed to avoid FSP-M reset. The default value of 0x01 is for MinPlatform */
    m_cfg->PchAdrEn = 0x02;

[Jonathan Zhang (Code Review)]

Jonathan Zhang has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/42334 )

Change subject: soc/intel/xeon_sp/cpx: code change for FSP ww24 release
......................................................................

Abandoned

The change was merged in another change [CB:41903]