Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/19544 )
Change subject: nb/intel/sandybridge/romstage: Use register name ......................................................................
nb/intel/sandybridge/romstage: Use register name
Use register name instead of hex value. No functional change.
Change-Id: Iacfe609f6454e6d58c9733f425377464238ce4a9 Signed-off-by: Patrick Rudolph siro@das-labor.org Reviewed-on: https://review.coreboot.org/19544 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Arthur Heymans arthur@aheymans.xyz Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net Reviewed-by: Sumeet R Pawnikar sumeet.r.pawnikar@intel.com --- M src/northbridge/intel/sandybridge/romstage.c 1 file changed, 2 insertions(+), 2 deletions(-)
Approvals: Sumeet R Pawnikar: Looks good to me, approved Arthur Heymans: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve build bot (Jenkins): Verified
diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 738e285..8608d5a 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -38,9 +38,9 @@ u8 reg8;
// reset rtc power status - reg8 = pci_read_config8(PCH_LPC_DEV, 0xa4); + reg8 = pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3); reg8 &= ~(1 << 2); - pci_write_config8(PCH_LPC_DEV, 0xa4, reg8); + pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3, reg8); }
/* Platform has no romstage entry point under mainboard directory,