Change in coreboot[master]: soc/intel/jasperlake: Enable USB2 PHY SUS PG for s0ix qualification

[Karthik Ramasubramanian (Code Review)]

Karthik Ramasubramanian has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49012 )

Change subject: soc/intel/jasperlake: Enable USB2 PHY SUS PG for s0ix qualification
......................................................................

soc/intel/jasperlake: Enable USB2 PHY SUS PG for s0ix qualification

USBSUSPGQDIS is a disqualifier bit which will allow platform
to enter s0ix even if USB2 PHY SUS is not power gated. Disabling this
bit will ensure that USB2 PHY SUS is power gated before entering s0ix.

BUG=b:175767084
BRANCH=dedede
TEST=s0ix works on drawcia and USB wake from s0ix works fine.

Change-Id: I20bad3f79141799c88a16272ea822b9e3dede504
Signed-off-by: Krishna Prasad Bhat 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49012
Tested-by: build bot (Jenkins) 
Reviewed-by: Furquan Shaikh 
Reviewed-by: Karthik Ramasubramanian 
Reviewed-by: Evan Green 
---
M src/soc/intel/jasperlake/finalize.c
M src/soc/intel/jasperlake/include/soc/pmc.h
2 files changed, 16 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, but someone else must approve
  Evan Green: Looks good to me, approved
  Karthik Ramasubramanian: Looks good to me, approved

diff --git a/src/soc/intel/jasperlake/finalize.c b/src/soc/intel/jasperlake/finalize.c
index d879db9..8219f0c 100644
--- a/src/soc/intel/jasperlake/finalize.c
+++ b/src/soc/intel/jasperlake/finalize.c
@@ -40,6 +40,8 @@

static void pch_finalize(void)
 {
+	uint32_t reg32;
+	uint8_t *pmcbase;
    config_t *config;

/* TCO Lock down */
@@ -62,6 +64,17 @@
    if (config->PmTimerDisabled)
    	pmc_disable_acpi_timer();

+	pmcbase = pmc_mmio_regs();
+	if (config->s0ix_enable) {
+		/*
+		 * Enable USBSUSPGQDIS qualification to ensure USB2 PHY SUS is power gated
+		 * before entering s0ix.
+		 */
+		reg32 = read32(pmcbase + CPPMVRIC3);
+		reg32 &= ~USBSUSPGQDIS;
+		write32(pmcbase + CPPMVRIC3, reg32);
+	}
+
    pch_handle_sideband(config);

pmc_clear_pmcon_sts();
diff --git a/src/soc/intel/jasperlake/include/soc/pmc.h b/src/soc/intel/jasperlake/include/soc/pmc.h
index 34172f8..e65e884 100644
--- a/src/soc/intel/jasperlake/include/soc/pmc.h
+++ b/src/soc/intel/jasperlake/include/soc/pmc.h
@@ -122,6 +122,9 @@
 #define CPPMVRIC			0x1B1C
 #define   XTALSDQDIS			(1 << 22)

+#define CPPMVRIC3			0x1E4C
+#define   USBSUSPGQDIS			(1 << 15)
+
 #define IRQ_REG				ACTL
 #define SCI_IRQ_ADJUST			0
 #define ACTL				0x1BD8