[XS] Change in coreboot[main]: soc/amd/phoenix/fch: only call gpp_clk_setup in FSP case

[Felix Held (Code Review)]

Attention is currently required from: Fred Reitberger, Jason Glenesk, Matt DeVillier.

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80295?usp=email )

Change subject: soc/amd/phoenix/fch: only call gpp_clk_setup in FSP case
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soc/amd/phoenix/fch: only call gpp_clk_setup in FSP case

The configuration of the PCIe clock generators in the FCH was moved from
the FSP to coreboot, since all registers are documented. This
initialization is however tightly integrated in the rest of the PCIe
init code inside the reference code. In the FSP case, this code was
manually removed. openSIL will do that part of the initialization so
that there's no coreboot-specific change needed in openSIL. This will
also avoid the problems caused by mismatching configurations done by the
coreboot code and the PCIe init part of the reference code.

Signed-off-by: Felix Held 
Change-Id: I6d64285a301ade6860c07e62dcb1a718e7a96644
---
M src/soc/amd/phoenix/fch.c
1 file changed, 3 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/80295/1

diff --git a/src/soc/amd/phoenix/fch.c b/src/soc/amd/phoenix/fch.c
index c2f0558..e9bc80a 100644
--- a/src/soc/amd/phoenix/fch.c
+++ b/src/soc/amd/phoenix/fch.c
@@ -200,7 +200,9 @@
    acpi_pm_gpe_add_events_print_events();
    gpio_add_events();

-	gpp_clk_setup();
+	if (CONFIG(PLATFORM_USES_FSP2_0))
+		gpp_clk_setup();
+
    fch_clk_output_48Mhz();
    cgpll_clock_gate_init();
 }