[S] Change in coreboot[master]: soc/intel/cmn/cpu: Add function to disable 3-strike CATERR

[Maximilian Brune (Code Review)]

Attention is currently required from: Tarun Tuli, Subrata Banik, Paul Menzel, Ivy Jian, Angel Pons, Ronak Kanabar.

Maximilian Brune has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74158 )

Change subject: soc/intel/cmn/cpu: Add function to disable 3-strike CATERR
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Patch Set 5:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/74158/comment/1c820686_92c2bb3c 
PS3, Line 8:
> >  I'm not here to explain what 3-stick error mean/does. One can refer to the appropriate document for that. 
> >
> > Than refer to it.
>
> Please try to understand we (googlers) working with Intel and have access to many docs (those are under NDA), we can't copy/paste some information from those docs and put them into the code review. Hence, we have to rely on the open source documentation and references. I can find some good reading here https://www.asset-intertech.com/resources/blog/2018/09/debug-of-intel-caterr... in public
>
> Also, Intel doc:576242 to have more information.

If you got the information from a NDA document, than of course you can just add intel document ID and be done with it. I would never suggest to break any kind of NDA. For me it just looked like this is general public knowledge (since it is also explained in the blog post you mentioned).
> > If I have to do a PCI BAR programming does that mean, I have to explain what is PCI and it's internal details ?
> >
> > Thats a poor comparison. PCI is a very broad and very well known subject in Firmware/Coreboot community. It is referenced in numerous coreboot patches and can therefore be seen as "common knowledge".
> > 3-three CATEER is a very specific thing that I assume is not known to "everyone" (at the very least its not known to me).
>
> I know this is a poor comparison but the point is hopefully clear, the purpose of the commit msg is not to educate about the technology. If the intention is to learn more on a certain topic, then a comment is more appropriate to know the source behind the technology like from where to learn more (isn't it ?). I can help here to share the possible information that I know. But as I said, some information are confidential and we can't just put those details to explain how CPU will collect more traces when 3-stike counter is disable vs enable.

I agree. A comment is much more useful for that.
> > I have wrote the commit msg to explain what this patch does
> >
> > Specifically I was missing the key information why disabling 3-three CATEER helps to do CPU traces. You say it does but you are not explaining why. At least one sentence about that would be enough for me.
> > So I basically have to trust, that what you say is true or google for half an hour to check -> review time is much longer
>
> I really don't know how to help here, those are very intel processor centric information and i won't be able to justify the expectation that you have here.

I think you misunderstood me. I don't expect you to write how CPU tracing works. Before reading this I was under the assumption that JTAG assisted hardware tracing is basically almost always possible, not matter what state the system is in. Therefore it was hard for me to grasp why a CATERR is preventing me from doing a proper CPU trace. Apparently according to the blog post, the JTAG debugger cannot put the hardware into probe mode then, but that wasn't obvious to me and therefore my confusion.

But I don't want to prolong your CL any longer and its only a minor problem for me anyway (despite how far the discussion went now).