Patch set updated for coreboot: skylake: Move I2C bus configuration to separate structure
Duncan Laurie (dlaurie@chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15104
-gerrit
commit 6c965f0be6b8ed8a5babd80dc28b3cfee25af77c Author: Duncan Laurie dlaurie@chromium.org Date: Mon Jun 6 17:21:00 2016 -0700
skylake: Move I2C bus configuration to separate structure
Move the existing I2C voltage configuration variable into a new structure that is equivalent, similar to how USB ports are configured.
This is to make room for additional I2C configuration options like bus speed and whether to enable the bus in early boot which are coming in a subsequent commit.
The affected mainboards are updated in this commit so it will build.
Signed-off-by: Duncan Laurie dlaurie@chromium.org Change-Id: Id2dea3df93e49000d60ddc66eb35d06cca6dd47e --- src/mainboard/google/chell/devicetree.cb | 5 ++--- src/mainboard/google/glados/devicetree.cb | 5 ++--- src/mainboard/google/lars/devicetree.cb | 3 ++- src/mainboard/intel/kunimitsu/devicetree.cb | 3 ++- src/soc/intel/skylake/chip.c | 5 +++-- src/soc/intel/skylake/chip.h | 16 ++++++++++++++-- 6 files changed, 25 insertions(+), 12 deletions(-)
diff --git a/src/mainboard/google/chell/devicetree.cb b/src/mainboard/google/chell/devicetree.cb index 428779a..349f724 100644 --- a/src/mainboard/google/chell/devicetree.cb +++ b/src/mainboard/google/chell/devicetree.cb @@ -153,6 +153,8 @@ chip soc/intel/skylake register "usb3_ports[2]" = "USB3_PORT_DEFAULT" # Type-A Port register "usb3_ports[3]" = "USB3_PORT_DEFAULT" # SD
+ register "i2c[4].voltage" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V + # Must leave UART0 enabled or SD/eMMC will not work as PCI register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, @@ -168,9 +170,6 @@ chip soc/intel/skylake [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }"
- # I2C4 is 1.8V - register "SerialIoI2cVoltage[4]" = "1" - # PL2 override 15W register "tdp_pl2_override" = "15"
diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index c4b89af..6518dbf 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -153,6 +153,8 @@ chip soc/intel/skylake register "usb3_ports[2]" = "USB3_PORT_DEFAULT" # Type-A Port 1 register "usb3_ports[3]" = "USB3_PORT_DEFAULT" # Type-A Port 2
+ register "i2c[4].voltage" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V + # Must leave UART0 enabled or SD/eMMC will not work as PCI register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, @@ -168,9 +170,6 @@ chip soc/intel/skylake [PchSerialIoIndexUart2] = PchSerialIoPci, }"
- # I2C4 is 1.8V - register "SerialIoI2cVoltage[4]" = "1" - # PL2 override 15W register "tdp_pl2_override" = "15"
diff --git a/src/mainboard/google/lars/devicetree.cb b/src/mainboard/google/lars/devicetree.cb index 5607ec8..fce0495 100644 --- a/src/mainboard/google/lars/devicetree.cb +++ b/src/mainboard/google/lars/devicetree.cb @@ -149,7 +149,8 @@ chip soc/intel/skylake register "usb3_ports[1]" = "USB3_PORT_DEFAULT" # SD register "usb3_ports[2]" = "USB3_PORT_DEFAULT" # Type-A Port (card) register "usb3_ports[3]" = "USB3_PORT_DEFAULT" # Type-A Port (board) - register "SerialIoI2cVoltage[4]" = "1" # I2C4 is 1.8V + + register "i2c[4].voltage" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V
# Must leave UART0 enabled or SD/eMMC will not work as PCI register "SerialIoDevMode" = "{ \ diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index 30039d8..b0d95f4 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -153,7 +153,8 @@ chip soc/intel/skylake register "usb3_ports[1]" = "USB3_PORT_DEFAULT" # Type-C Port 2 register "usb3_ports[2]" = "USB3_PORT_DEFAULT" # Type-A Port (card) register "usb3_ports[3]" = "USB3_PORT_DEFAULT" # Type-A Port (board) - register "SerialIoI2cVoltage[4]" = "1" # I2C4 is 1.8V + + register "i2c[4].voltage" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V
# Must leave UART0 enabled or SD/eMMC will not work as PCI register "SerialIoDevMode" = "{ \ diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index f990d2b..7bbf336 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -415,8 +415,9 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params) params->SerialIrqConfigStartFramePulse = config->SerialIrqConfigStartFramePulse;
params->SkipMpInit = config->FspSkipMpInit; - memcpy(params->SerialIoI2cVoltage, config->SerialIoI2cVoltage, - sizeof(params->SerialIoI2cVoltage)); + + for (i = 0; i < ARRAY_SIZE(config->i2c); i++) + params->SerialIoI2cVoltage[i] = config->i2c[i].voltage;
/* * To disable Heci, the Psf needs to be left unlocked diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 2db84b7..1d3113f 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -29,6 +29,18 @@ #include <soc/usb.h> #include <soc/vr_config.h>
+#define SKYLAKE_I2C_DEV_MAX 6 + +enum skylake_i2c_voltage { + I2C_VOLTAGE_3V3, + I2C_VOLTAGE_1V8 +}; + +struct skylake_i2c_config { + /* Bus voltage level, default is 3.3V */ + enum skylake_i2c_voltage voltage; +}; + struct soc_intel_skylake_config { /* * Interrupt Routing configuration @@ -179,8 +191,8 @@ struct soc_intel_skylake_config { */ u8 SerialIoDevMode[PchSerialIoIndexMax];
- /* I2C voltage select. Value: 0: 3.3V , 1: 1.8V.*/ - u8 SerialIoI2cVoltage[6]; + /* I2C */ + struct skylake_i2c_config i2c[SKYLAKE_I2C_DEV_MAX];
/* Camera */ u8 Cio2Enable;
-
Duncan Laurie