Change in coreboot[master]: [WIP]coreboot_table: Add a record to hold the PCIE BASE + Total bus n...
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35879 )
Change subject: [WIP]coreboot_table: Add a record to hold the PCIE BASE + Total bus number ......................................................................
[WIP]coreboot_table: Add a record to hold the PCIE BASE + Total bus number
This can be useful for PCI MMCONF access in payloads.
Change-Id: I1c31fc439896715fb69a627672499ffb4112ee51 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/commonlib/include/commonlib/coreboot_tables.h M src/lib/coreboot_table.c 2 files changed, 22 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/35879/1
diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index 6816670..3182e9e 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -90,6 +90,7 @@ LB_TAG_MMC_INFO = 0x0035, LB_TAG_TCPA_LOG = 0x0036, LB_TAG_FMAP = 0x0037, + LB_TAG_PCIE_BASE = 0x0038, LB_TAG_CMOS_OPTION_TABLE = 0x00c8, LB_TAG_OPTION = 0x00c9, LB_TAG_OPTION_ENUM = 0x00ca, @@ -429,6 +430,13 @@ struct mac_address mac_addrs[0]; };
+struct lb_pcie_info { + uint32_t tag; + uint32_t size; + uint64_t base; + uint32_t bus_number; +}; + #define MAX_SERIALNO_LENGTH 32
/* The following structures are for the cmos definitions table */ diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index d3576e6..6294762 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -452,6 +452,17 @@ */ void __weak lb_spi_flash(struct lb_header *header) { /* NOOP */ }
+static void lb_pcie_base(struct lb_header *header) +{ + struct lb_pcie_base *rec; + rec = (struct lb_pcie_base *)lb_new_record(header); + rec->tab = LB_TAG_PCIE_BASE; + rec->size = sizeof(*rec); + rec->base = CONFIG_MMCONF_BASE_ADDRESS; + /* Coreboot only populates this value on AMD and VIA for now... */ + rec->bus_number = CONFIG_MMCONF_BUS_NUMBER; +} + static struct lb_forward *lb_forward(struct lb_header *header, struct lb_header *next_header) { @@ -587,6 +598,9 @@ /* Add all cbmem entries into the coreboot tables. */ cbmem_add_records_to_cbtable(head);
+ /* Add PCIE Base */ + lb_pcie_base(head); + /* Remember where my valid memory ranges are */ return lb_table_fini(head); }
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35879 )
Change subject: [WIP]coreboot_table: Add a record to hold the PCIE BASE + Total bus number ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35879/3/src/lib/coreboot_table.c File src/lib/coreboot_table.c:
https://review.coreboot.org/c/coreboot/+/35879/3/src/lib/coreboot_table.c@46... PS3, Line 462: /* Coreboot only populates this value on AMD and VIA for now... */ comment seems no longer true
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35879 )
Change subject: [WIP]coreboot_table: Add a record to hold the PCIE BASE + Total bus number ......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/c/coreboot/+/35879/3/src/lib/coreboot_table.c File src/lib/coreboot_table.c:
https://review.coreboot.org/c/coreboot/+/35879/3/src/lib/coreboot_table.c@45... PS3, Line 459: tab tag
https://review.coreboot.org/c/coreboot/+/35879/3/src/lib/coreboot_table.c@46... PS3, Line 462: /* Coreboot only populates this value on AMD and VIA for now... */
comment seems no longer true
still WIP.
Arthur Heymans has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/35879 )
Change subject: [WIP]coreboot_table: Add a record to hold the PCIE BASE + Total bus number ......................................................................
Abandoned
Patches from mediatek do it better.
-
Arthur Heymans (Code Review) -
Patrick Rudolph (Code Review)