Change in coreboot[master]: nb/intel/*: Use 2M TSEG instead of 8M on pre-arrandale hardware

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/27873

Change subject: nb/intel/*: Use 2M TSEG instead of 8M on pre-arrandale hardware
......................................................................

nb/intel/*: Use 2M TSEG instead of 8M on pre-arrandale hardware

8M was set in the assumption that at least 4M was needed for IED
(Intel Enhanced Debug) , but this is not true.

The SMRR MTRR's need to have TSEG aligned to its size which is easier when TSEG
is only 2M. Also at most 6M of RAM more becomes available for use.

Change-Id: I4b114c8dc13699b3c034f0a7060181d9d590737b
Signed-off-by: Arthur Heymans 
---
M src/northbridge/intel/gm45/raminit.c
M src/northbridge/intel/i945/early_init.c
M src/northbridge/intel/pineview/raminit.c
M src/northbridge/intel/x4x/raminit_ddr23.c
4 files changed, 9 insertions(+), 9 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/27873/1

diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c
index 08f954d..61a2b4e 100644
--- a/src/northbridge/intel/gm45/raminit.c
+++ b/src/northbridge/intel/gm45/raminit.c
@@ -1242,12 +1242,12 @@

uma_sizem = (gms_sizek + gsm_sizek) >> 10;
    	}
-		/* TSEG 8M */
+		/* TSEG 2M */
    	u8 reg8 = pci_read_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC);
    	reg8 &= ~0x7;
-		reg8 |= (2 << 1) | (1 << 0); /* 8M and TSEG_Enable */
+		reg8 |= (1 << 1) | (1 << 0); /* 2M and TSEG_Enable */
    	pci_write_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC, reg8);
-		uma_sizem += 8;
+		uma_sizem += 2;
    }

const unsigned int mmio_size = get_mmio_size();
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index 7de2c73..8e68af5 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -194,7 +194,7 @@

reg8 = pci_read_config8(PCI_DEV(0, 0, 0), ESMRAMC);
    reg8 &= ~0x7;
-	reg8 |= (2 << 1) | (1 << 0); /* 8M and TSEG_Enable */
+	reg8 |= (1 << 1) | (1 << 0); /* 2M and TSEG_Enable */
    pci_write_config8(PCI_DEV(0, 0, 0), ESMRAMC, reg8);

/* Set C0000-FFFFF to access RAM on both reads and writes */
diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c
index 66f0a10..59eadc3 100644
--- a/src/northbridge/intel/pineview/raminit.c
+++ b/src/northbridge/intel/pineview/raminit.c
@@ -2039,7 +2039,7 @@
    gttsize = ggc_to_gtt[(ggc & 0x300) >> 8];
    tom = s->channel_capacity[0];

-	tsegsize = 0x8; // 8MB
+	tsegsize = 0x2; // 2MB
    mmiosize = 0x400; // 1GB

reclaim = false;
@@ -2076,7 +2076,7 @@

u8 reg8 = pci_read_config8(PCI_DEV(0, 0, 0), ESMRAMC);
    reg8 &= ~0x7;
-	reg8 |= (2 << 1) | (1 << 0); /* 8M and TSEG_Enable */
+	reg8 |= (1 << 1) | (1 << 0); /* 2M and TSEG_Enable */
    pci_write_config8(PCI_DEV(0, 0, 0), ESMRAMC, reg8);

printk(BIOS_DEBUG, "GBSM (igd) = verified %08x (written %08x)\n",
diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c
index c445cad..a788dd9 100644
--- a/src/northbridge/intel/x4x/raminit_ddr23.c
+++ b/src/northbridge/intel/x4x/raminit_ddr23.c
@@ -1722,7 +1722,7 @@
    ggc = pci_read_config16(PCI_DEV(0, 0, 0), 0x52);
    gfxsize = ggc2uma[(ggc & 0xf0) >> 4];
    gttsize = ggc2gtt[(ggc & 0xf00) >> 8];
-	tsegsize = 8; // 8MB TSEG
+	tsegsize = 2; // 2MB TSEG
    mmiosize = 0x800; // 2GB MMIO
    umasizem = gfxsize + gttsize + tsegsize;
    mmiostart = 0x1000 - mmiosize + umasizem;
@@ -1759,10 +1759,10 @@
    pci_write_config16(PCI_DEV(0, 0, 0), 0xa2, touud);
    pci_write_config32(PCI_DEV(0, 0, 0), 0xa4, gfxbase << 20);
    pci_write_config32(PCI_DEV(0, 0, 0), 0xa8, gttbase << 20);
-	/* Enable and set tseg size to 8M */
+	/* Enable and set tseg size to 2M */
    reg8 = pci_read_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC);
    reg8 &= ~0x7;
-	reg8 |= (2 << 1) | (1 << 0); /* 8M and TSEG_Enable */
+	reg8 |= (1 << 1) | (1 << 0); /* 2M and TSEG_Enable */
    pci_write_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC, reg8);
    pci_write_config32(PCI_DEV(0, 0, 0), 0xac, tsegbase << 20);
 }