Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/76997?usp=email )
Change subject: mb/roda/rv11: Post-Haswell cleanup ......................................................................
mb/roda/rv11: Post-Haswell cleanup
With Haswell-style SPD info in place, drop mainboard_get_spd().
For MRC raminit path, fill only data that cannot be had elsewhere instead of redoing the entire PEI data structure.
Drop unneeded includes.
Change-Id: I74b53cc43a610d7ecfd1ed50c93999cd98f2eb77 Signed-off-by: Keith Hui buurin@gmail.com --- M src/mainboard/roda/rv11/variants/rv11/early_init.c M src/mainboard/roda/rv11/variants/rw11/early_init.c 2 files changed, 58 insertions(+), 116 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/76997/1
diff --git a/src/mainboard/roda/rv11/variants/rv11/early_init.c b/src/mainboard/roda/rv11/variants/rv11/early_init.c index 155152c..129816c 100644 --- a/src/mainboard/roda/rv11/variants/rv11/early_init.c +++ b/src/mainboard/roda/rv11/variants/rv11/early_init.c @@ -1,62 +1,39 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <arch/hpet.h> -#include <stdint.h> #include <northbridge/intel/sandybridge/raminit.h> -#include <northbridge/intel/sandybridge/raminit_native.h> -#include <northbridge/intel/sandybridge/sandybridge.h> +// #include <northbridge/intel/sandybridge/sandybridge.h> #include <southbridge/intel/bd82x6x/pch.h>
-void mainboard_fill_pei_data(struct pei_data *const pei_data) +void mainboard_fill_pei_data(struct pei_data *pei) { - const struct pei_data pei_data_template = { - .pei_version = PEI_VERSION, - .mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE, - .dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE, - .epbar = CONFIG_FIXED_EPBAR_MMIO_BASE, - .pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS, - .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = HPET_BASE_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBA, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .thermalbase = 0xfed08000, - .system_type = 0, // 0 Mobile, 1 Desktop/Server - .tseg_size = CONFIG_SMM_TSEG_SIZE, - .spd_addresses = { 0xA0, 0x00, 0xA4, 0x00 }, - .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, - .ec_present = 1, - .gbe_enable = 1, - .ddr3lv_support = 0, - .max_ddr3_freq = 1600, - .usb_port_config = { - /* Enabled / OC PIN / Length */ - { 1, 0, 0x0040 }, /* P00: 1st USB3 (OC #0) */ - { 1, 4, 0x0040 }, /* P01: 2nd USB3 (OC #4) */ - { 1, 1, 0x0080 }, /* P02: 1st Multibay USB3 (OC #1) */ - { 1, 2, 0x0080 }, /* P03: 2nd Multibay USB3 (OC #2) */ - { 1, 8, 0x0040 }, /* P04: MiniPCIe 1 USB2 (no OC) */ - { 1, 8, 0x0040 }, /* P05: MiniPCIe 2 USB2 (no OC) */ - { 1, 8, 0x0040 }, /* P06: MiniPCIe 3 USB2 (no OC) */ - { 1, 8, 0x0040 }, /* P07: GPS USB2 (no OC) */ - { 1, 8, 0x0040 }, /* P08: MiniPCIe 4 USB2 (no OC) */ - { 1, 3, 0x0040 }, /* P09: Express Card USB2 (OC #3) */ - { 1, 8, 0x0040 }, /* P10: SD card reader USB2 (no OC) */ - { 1, 8, 0x0040 }, /* P11: Sensors Hub? USB2 (no OC) */ - { 1, 8, 0x0040 }, /* P12: Touch Screen USB2 (no OC) */ - { 1, 5, 0x0040 }, /* P13: reserved? USB2 (OC #5) */ - }, - .usb3 = { - .mode = 3, /* Smart Auto? */ - .hs_port_switch_mask = 0xf, /* All four ports. */ - .preboot_support = 1, /* preOS driver? */ - .xhci_streams = 1, /* Enable. */ - }, - .pcie_init = 1, + uint16_t usbcfg[16][3] = { + /* Enabled / OC PIN / Length */ + { 1, 0, 0x0040 }, /* P00: 1st USB3 (OC #0) */ + { 1, 4, 0x0040 }, /* P01: 2nd USB3 (OC #4) */ + { 1, 1, 0x0080 }, /* P02: 1st Multibay USB3 (OC #1) */ + { 1, 2, 0x0080 }, /* P03: 2nd Multibay USB3 (OC #2) */ + { 1, 8, 0x0040 }, /* P04: MiniPCIe 1 USB2 (no OC) */ + { 1, 8, 0x0040 }, /* P05: MiniPCIe 2 USB2 (no OC) */ + { 1, 8, 0x0040 }, /* P06: MiniPCIe 3 USB2 (no OC) */ + { 1, 8, 0x0040 }, /* P07: GPS USB2 (no OC) */ + { 1, 8, 0x0040 }, /* P08: MiniPCIe 4 USB2 (no OC) */ + { 1, 3, 0x0040 }, /* P09: Express Card USB2 (OC #3) */ + { 1, 8, 0x0040 }, /* P10: SD card reader USB2 (no OC) */ + { 1, 8, 0x0040 }, /* P11: Sensors Hub? USB2 (no OC) */ + { 1, 8, 0x0040 }, /* P12: Touch Screen USB2 (no OC) */ + { 1, 5, 0x0040 }, /* P13: reserved? USB2 (OC #5) */ }; - *pei_data = pei_data_template; + + memcpy(pei->usb_port_config, &usbcfg, sizeof(usbcfg)); + + pei->max_ddr3_freq = 1600; + pei->ec_present = 1; + pei->gbe_enable = 1; + pei->pcie_init = 1; + pei->usb3.hs_port_switch_mask = 0xf; + pei->usb3.mode = 3; + pei->usb3.preboot_support = 1; + pei->usb3.xhci_streams = 1; }
const struct southbridge_usb_port mainboard_usb_ports[] = { @@ -77,12 +54,6 @@ { 1, 0, 5 }, /* P13: reserved? USB2 (OC #5) */ };
-void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[2], 0x52, id_only); -} - void mb_get_spd_map(struct spd_info *spdi) { spdi->addresses[0] = 0x50; diff --git a/src/mainboard/roda/rv11/variants/rw11/early_init.c b/src/mainboard/roda/rv11/variants/rw11/early_init.c index 84bf2d1..8dadf8a 100644 --- a/src/mainboard/roda/rv11/variants/rw11/early_init.c +++ b/src/mainboard/roda/rv11/variants/rw11/early_init.c @@ -6,8 +6,7 @@ #include <device/pnp_ops.h> #include <device/pnp.h> #include <northbridge/intel/sandybridge/raminit.h> -#include <northbridge/intel/sandybridge/raminit_native.h> -#include <northbridge/intel/sandybridge/sandybridge.h> +// include <northbridge/intel/sandybridge/sandybridge.h> #include <southbridge/intel/bd82x6x/pch.h> #include <superio/ite/it8783ef/it8783ef.h> #include <superio/ite/common/ite.h> @@ -37,56 +36,36 @@ pnp_exit_conf_state(dev); }
-void mainboard_fill_pei_data(struct pei_data *const pei_data) +void mainboard_fill_pei_data(struct pei_data *pei) { - const struct pei_data pei_data_template = { - .pei_version = PEI_VERSION, - .mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE, - .dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE, - .epbar = CONFIG_FIXED_EPBAR_MMIO_BASE, - .pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS, - .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = HPET_BASE_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBA, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .thermalbase = 0xfed08000, - .system_type = 0, // 0 Mobile, 1 Desktop/Server - .tseg_size = CONFIG_SMM_TSEG_SIZE, - .spd_addresses = { 0xA0, 0xA2, 0xA4, 0xA6 }, - .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, - .ec_present = 1, - .gbe_enable = 1, - .ddr3lv_support = 0, - .max_ddr3_freq = 1600, - .usb_port_config = { - /* Enabled / OC PIN / Length */ - { 1, 0, 0x0080 }, /* P00: 1st (left) USB3 (OC #0) */ - { 1, 0, 0x0080 }, /* P01: 2nd (left) USB3 (OC #0) */ - { 1, 1, 0x0080 }, /* P02: 1st Multibay USB3 (OC #1) */ - { 1, 1, 0x0080 }, /* P03: 2nd Multibay USB3 (OC #1) */ - { 1, 8, 0x0040 }, /* P04: MiniPCIe 1 USB2 (no OC) */ - { 1, 8, 0x0040 }, /* P05: MiniPCIe 2 USB2 (no OC) */ - { 1, 8, 0x0040 }, /* P06: USB Hub x4 USB2 (no OC) */ - { 1, 8, 0x0040 }, /* P07: MiniPCIe 4 USB2 (no OC) */ - { 1, 8, 0x0080 }, /* P08: SD card reader USB2 (no OC) */ - { 1, 4, 0x0080 }, /* P09: 3rd (right) USB2 (OC #4) */ - { 1, 5, 0x0040 }, /* P10: 4th (right) USB2 (OC #5) */ - { 1, 8, 0x0040 }, /* P11: 3rd Multibay USB2 (no OC) */ - { 1, 8, 0x0080 }, /* P12: misc internal USB2 (no OC) */ - { 1, 6, 0x0080 }, /* P13: misc internal USB2 (OC #6) */ - }, - .usb3 = { - .mode = 3, /* Smart Auto? */ - .hs_port_switch_mask = 0xf, /* All four ports. */ - .preboot_support = 1, /* preOS driver? */ - .xhci_streams = 1, /* Enable. */ - }, - .pcie_init = 1, + uint16_t usbcfg[16][3] = { + /* Enabled / OC PIN / Length */ + { 1, 0, 0x0080 }, /* P00: 1st (left) USB3 (OC #0) */ + { 1, 0, 0x0080 }, /* P01: 2nd (left) USB3 (OC #0) */ + { 1, 1, 0x0080 }, /* P02: 1st Multibay USB3 (OC #1) */ + { 1, 1, 0x0080 }, /* P03: 2nd Multibay USB3 (OC #1) */ + { 1, 8, 0x0040 }, /* P04: MiniPCIe 1 USB2 (no OC) */ + { 1, 8, 0x0040 }, /* P05: MiniPCIe 2 USB2 (no OC) */ + { 1, 8, 0x0040 }, /* P06: USB Hub x4 USB2 (no OC) */ + { 1, 8, 0x0040 }, /* P07: MiniPCIe 4 USB2 (no OC) */ + { 1, 8, 0x0080 }, /* P08: SD card reader USB2 (no OC) */ + { 1, 4, 0x0080 }, /* P09: 3rd (right) USB2 (OC #4) */ + { 1, 5, 0x0040 }, /* P10: 4th (right) USB2 (OC #5) */ + { 1, 8, 0x0040 }, /* P11: 3rd Multibay USB2 (no OC) */ + { 1, 8, 0x0080 }, /* P12: misc internal USB2 (no OC) */ + { 1, 6, 0x0080 }, /* P13: misc internal USB2 (OC #6) */ }; - *pei_data = pei_data_template; + + memcpy(pei->usb_port_config, &usbcfg, sizeof(usbcfg)); + + pei->max_ddr3_freq = 1600; + pei->ec_present = 1; + pei->gbe_enable = 1; + pei->pcie_init = 1; + pei->usb3.hs_port_switch_mask = 0xf; + pei->usb3.mode = 3; + pei->usb3.preboot_support = 1; + pei->usb3.xhci_streams = 1; }
const struct southbridge_usb_port mainboard_usb_ports[] = { @@ -107,14 +86,6 @@ { 1, 1, 6 }, /* P13: misc internal USB2 (OC #6) */ };
-void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[1], 0x51, id_only); - read_spd(&spd[2], 0x52, id_only); - read_spd(&spd[3], 0x53, id_only); -} - void mb_get_spd_map(struct spd_info *spdi) { spdi->addresses[0] = 0x50;
-
Keith Hui (Code Review)