Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36368 )
Change subject: soc/qualcomm: Link cbmem.c only in romstage ......................................................................
soc/qualcomm: Link cbmem.c only in romstage
Change-Id: I008fcca024fecf462c4b550b8dedbf4b06e491b8 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/mainboard/google/gale/mmu.c M src/mainboard/google/storm/mmu.c M src/soc/qualcomm/ipq40xx/Makefile.inc M src/soc/qualcomm/ipq40xx/cbmem.c M src/soc/qualcomm/ipq806x/Makefile.inc M src/soc/qualcomm/ipq806x/cbmem.c 6 files changed, 7 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/36368/1
diff --git a/src/mainboard/google/gale/mmu.c b/src/mainboard/google/gale/mmu.c index bf46f7a..7ac8b92 100644 --- a/src/mainboard/google/gale/mmu.c +++ b/src/mainboard/google/gale/mmu.c @@ -38,7 +38,8 @@ /* Map DMA memory */ mmu_config_range(DMA_START, DMA_SIZE, DCACHE_OFF); /* Mark cbmem backing store as ready. */ - ipq_cbmem_backing_store_ready(); + if (ENV_ROMSTAGE) + ipq_cbmem_backing_store_ready(); } else { mmu_disable_range(DRAM_START, DRAM_SIZE); /* Map DMA memory */ diff --git a/src/mainboard/google/storm/mmu.c b/src/mainboard/google/storm/mmu.c index 9750cc1..3f1515a 100644 --- a/src/mainboard/google/storm/mmu.c +++ b/src/mainboard/google/storm/mmu.c @@ -35,10 +35,9 @@ mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK); /* Map DMA memory */ mmu_config_range(DMA_START, DMA_SIZE, DCACHE_OFF); -#if ENV_ROMSTAGE - /* Mark cbmem backing store as ready. */ - ipq_cbmem_backing_store_ready(); -#endif + if (ENV_ROMSTAGE) + /* Mark cbmem backing store as ready. */ + ipq_cbmem_backing_store_ready(); } else { mmu_disable_range(DRAM_START, DRAM_SIZE); /* Map DMA memory */ diff --git a/src/soc/qualcomm/ipq40xx/Makefile.inc b/src/soc/qualcomm/ipq40xx/Makefile.inc index 6447acf..b20ae24 100644 --- a/src/soc/qualcomm/ipq40xx/Makefile.inc +++ b/src/soc/qualcomm/ipq40xx/Makefile.inc @@ -16,7 +16,6 @@ ifeq ($(CONFIG_SOC_QC_IPQ40XX),y)
bootblock-y += clock.c -bootblock-y += cbmem.c bootblock-y += gpio.c bootblock-$(CONFIG_SPI_FLASH) += spi.c bootblock-y += timer.c @@ -43,7 +42,6 @@ romstage-y += qup.c
ramstage-y += blobs_init.c -ramstage-y += cbmem.c ramstage-y += clock.c ramstage-y += gpio.c ramstage-y += lcc.c diff --git a/src/soc/qualcomm/ipq40xx/cbmem.c b/src/soc/qualcomm/ipq40xx/cbmem.c index bed6fce..2c4def6 100644 --- a/src/soc/qualcomm/ipq40xx/cbmem.c +++ b/src/soc/qualcomm/ipq40xx/cbmem.c @@ -31,7 +31,7 @@ * with components that utilize cbmem in romstage (e.g. vboot_locator * for loading ipq blobs before DRAM is initialized). */ - if (ENV_ROMSTAGE && (cbmem_backing_store_ready == 0)) + if (cbmem_backing_store_ready == 0) return NULL;
return _memlayout_cbmem_top; diff --git a/src/soc/qualcomm/ipq806x/Makefile.inc b/src/soc/qualcomm/ipq806x/Makefile.inc index 1fd134a..67d54d2 100644 --- a/src/soc/qualcomm/ipq806x/Makefile.inc +++ b/src/soc/qualcomm/ipq806x/Makefile.inc @@ -42,7 +42,6 @@ romstage-y += qup.c
ramstage-y += blobs_init.c -ramstage-y += cbmem.c ramstage-y += clock.c ramstage-y += gpio.c ramstage-y += lcc.c diff --git a/src/soc/qualcomm/ipq806x/cbmem.c b/src/soc/qualcomm/ipq806x/cbmem.c index 564f538..38f3d73 100644 --- a/src/soc/qualcomm/ipq806x/cbmem.c +++ b/src/soc/qualcomm/ipq806x/cbmem.c @@ -32,7 +32,7 @@ * (e.g. vboot_locator for loading ipq blobs before DRAM is * initialized). */ - if (ENV_ROMSTAGE && (cbmem_backing_store_ready == 0)) + if (cbmem_backing_store_ready == 0) return NULL;
return _memlayout_cbmem_top;
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36368 )
Change subject: soc/qualcomm: Link cbmem.c only in romstage ......................................................................
Patch Set 10: Code-Review+2
Hello Patrick Rudolph, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36368
to look at the new patch set (#24).
Change subject: soc/qualcomm: Link cbmem.c only in romstage ......................................................................
soc/qualcomm: Link cbmem.c only in romstage
Change-Id: I008fcca024fecf462c4b550b8dedbf4b06e491b8 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/mainboard/google/gale/mmu.c M src/mainboard/google/storm/mmu.c M src/soc/qualcomm/ipq40xx/Makefile.inc M src/soc/qualcomm/ipq40xx/cbmem.c M src/soc/qualcomm/ipq806x/Makefile.inc M src/soc/qualcomm/ipq806x/cbmem.c 6 files changed, 7 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/36368/24
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36368 )
Change subject: soc/qualcomm: Link cbmem.c only in romstage ......................................................................
Patch Set 24: Code-Review+2
Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/36368 )
Change subject: soc/qualcomm: Link cbmem.c only in romstage ......................................................................
soc/qualcomm: Link cbmem.c only in romstage
Change-Id: I008fcca024fecf462c4b550b8dedbf4b06e491b8 Signed-off-by: Arthur Heymans arthur@aheymans.xyz Reviewed-on: https://review.coreboot.org/c/coreboot/+/36368 Reviewed-by: Nico Huber nico.h@gmx.de Reviewed-by: Patrick Rudolph siro@das-labor.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/gale/mmu.c M src/mainboard/google/storm/mmu.c M src/soc/qualcomm/ipq40xx/Makefile.inc M src/soc/qualcomm/ipq40xx/cbmem.c M src/soc/qualcomm/ipq806x/Makefile.inc M src/soc/qualcomm/ipq806x/cbmem.c 6 files changed, 7 insertions(+), 10 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Patrick Rudolph: Looks good to me, approved
diff --git a/src/mainboard/google/gale/mmu.c b/src/mainboard/google/gale/mmu.c index bf46f7a..7ac8b92 100644 --- a/src/mainboard/google/gale/mmu.c +++ b/src/mainboard/google/gale/mmu.c @@ -38,7 +38,8 @@ /* Map DMA memory */ mmu_config_range(DMA_START, DMA_SIZE, DCACHE_OFF); /* Mark cbmem backing store as ready. */ - ipq_cbmem_backing_store_ready(); + if (ENV_ROMSTAGE) + ipq_cbmem_backing_store_ready(); } else { mmu_disable_range(DRAM_START, DRAM_SIZE); /* Map DMA memory */ diff --git a/src/mainboard/google/storm/mmu.c b/src/mainboard/google/storm/mmu.c index 9750cc1..3f1515a 100644 --- a/src/mainboard/google/storm/mmu.c +++ b/src/mainboard/google/storm/mmu.c @@ -35,10 +35,9 @@ mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK); /* Map DMA memory */ mmu_config_range(DMA_START, DMA_SIZE, DCACHE_OFF); -#if ENV_ROMSTAGE - /* Mark cbmem backing store as ready. */ - ipq_cbmem_backing_store_ready(); -#endif + if (ENV_ROMSTAGE) + /* Mark cbmem backing store as ready. */ + ipq_cbmem_backing_store_ready(); } else { mmu_disable_range(DRAM_START, DRAM_SIZE); /* Map DMA memory */ diff --git a/src/soc/qualcomm/ipq40xx/Makefile.inc b/src/soc/qualcomm/ipq40xx/Makefile.inc index 6447acf..b20ae24 100644 --- a/src/soc/qualcomm/ipq40xx/Makefile.inc +++ b/src/soc/qualcomm/ipq40xx/Makefile.inc @@ -16,7 +16,6 @@ ifeq ($(CONFIG_SOC_QC_IPQ40XX),y)
bootblock-y += clock.c -bootblock-y += cbmem.c bootblock-y += gpio.c bootblock-$(CONFIG_SPI_FLASH) += spi.c bootblock-y += timer.c @@ -43,7 +42,6 @@ romstage-y += qup.c
ramstage-y += blobs_init.c -ramstage-y += cbmem.c ramstage-y += clock.c ramstage-y += gpio.c ramstage-y += lcc.c diff --git a/src/soc/qualcomm/ipq40xx/cbmem.c b/src/soc/qualcomm/ipq40xx/cbmem.c index 972c625..9970758 100644 --- a/src/soc/qualcomm/ipq40xx/cbmem.c +++ b/src/soc/qualcomm/ipq40xx/cbmem.c @@ -31,7 +31,7 @@ * with components that utilize cbmem in romstage (e.g. vboot_locator * for loading ipq blobs before DRAM is initialized). */ - if (ENV_ROMSTAGE && (cbmem_backing_store_ready == 0)) + if (cbmem_backing_store_ready == 0) return NULL;
return _memlayout_cbmem_top; diff --git a/src/soc/qualcomm/ipq806x/Makefile.inc b/src/soc/qualcomm/ipq806x/Makefile.inc index 1fd134a..67d54d2 100644 --- a/src/soc/qualcomm/ipq806x/Makefile.inc +++ b/src/soc/qualcomm/ipq806x/Makefile.inc @@ -42,7 +42,6 @@ romstage-y += qup.c
ramstage-y += blobs_init.c -ramstage-y += cbmem.c ramstage-y += clock.c ramstage-y += gpio.c ramstage-y += lcc.c diff --git a/src/soc/qualcomm/ipq806x/cbmem.c b/src/soc/qualcomm/ipq806x/cbmem.c index 6dc92a0..32f303e 100644 --- a/src/soc/qualcomm/ipq806x/cbmem.c +++ b/src/soc/qualcomm/ipq806x/cbmem.c @@ -32,7 +32,7 @@ * (e.g. vboot_locator for loading ipq blobs before DRAM is * initialized). */ - if (ENV_ROMSTAGE && (cbmem_backing_store_ready == 0)) + if (cbmem_backing_store_ready == 0) return NULL;
return _memlayout_cbmem_top;
-
Arthur Heymans (Code Review) -
Nico Huber (Code Review)
-
Patrick Rudolph (Code Review)