Wonkyu Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39710 )
Change subject: [TEST]soc/intel/tigerlake: unlock RTC memory ......................................................................
[TEST]soc/intel/tigerlake: unlock RTC memory
Unlock RTC memory for OS to update info
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: I63cec8a718285f424914e426d0399ed821588dfd --- M src/soc/intel/tigerlake/fsp_params_tgl.c 1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/39710/1
diff --git a/src/soc/intel/tigerlake/fsp_params_tgl.c b/src/soc/intel/tigerlake/fsp_params_tgl.c index a8be407..31968d9 100644 --- a/src/soc/intel/tigerlake/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/fsp_params_tgl.c @@ -107,6 +107,10 @@ for (i = 0; i < 8; i++) params->IomTypeCPortPadCfg[i] = 0x09000000;
+ /* TODO: before UPD is avaialbe for RtcMemoryLock (offset:0x0621) */ + /* params->RtcMemoryLock = 0 */ + params->Reserved25[2] = 0; + /* USB */ for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { params->PortUsb20Enable[i] = config->usb2_ports[i].enable;
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39710 )
Change subject: [TEST]soc/intel/tigerlake: unlock RTC memory ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39710/1/src/soc/intel/tigerlake/fsp... File src/soc/intel/tigerlake/fsp_params_tgl.c:
https://review.coreboot.org/c/coreboot/+/39710/1/src/soc/intel/tigerlake/fsp... PS1, Line 110: /* TODO: before UPD is avaialbe for RtcMemoryLock (offset:0x0621) */ 'avaialbe' may be misspelled - perhaps 'available'?
Wonkyu Kim has removed Patrick Rudolph from this change. ( https://review.coreboot.org/c/coreboot/+/39710 )
Change subject: [TEST]soc/intel/tigerlake: unlock RTC memory ......................................................................
Removed reviewer Patrick Rudolph.
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39710 )
Change subject: soc/intel/tigerlake: unlock RTC memory ......................................................................
Patch Set 4: Code-Review+1
(1 comment)
This change is ready for review.
https://review.coreboot.org/c/coreboot/+/39710/1/src/soc/intel/tigerlake/fsp... File src/soc/intel/tigerlake/fsp_params_tgl.c:
https://review.coreboot.org/c/coreboot/+/39710/1/src/soc/intel/tigerlake/fsp... PS1, Line 110: /* TODO: before UPD is avaialbe for RtcMemoryLock (offset:0x0621) */
'avaialbe' may be misspelled - perhaps 'available'?
Ack
Wonkyu Kim has removed a vote from this change. ( https://review.coreboot.org/c/coreboot/+/39710 )
Change subject: soc/intel/tigerlake: unlock RTC memory ......................................................................
Removed Code-Review+1 by Wonkyu Kim wonkyu.kim@intel.com
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39710 )
Change subject: soc/intel/tigerlake: unlock RTC memory ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39710/1/src/soc/intel/tigerlake/fsp... File src/soc/intel/tigerlake/fsp_params_tgl.c:
https://review.coreboot.org/c/coreboot/+/39710/1/src/soc/intel/tigerlake/fsp... PS1, Line 110: /* TODO: before UPD is avaialbe for RtcMemoryLock (offset:0x0621) */
Ack
Done
Hello build bot (Jenkins), Shaunak Saha, Francois Toguo Fotso, Srinidhi N Kaushik, Raj Astekar, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#6).
Change subject: soc/intel/tigerlake: unlock RTC memory ......................................................................
soc/intel/tigerlake: unlock RTC memory
Unlock RTC memory for OS to update info
BUG=b:153108724 BRANCH=none TEST=build and boot ripto/volteer and check below crossystem command which use RTC memory. crossystem recovery_request=193
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: I63cec8a718285f424914e426d0399ed821588dfd --- M src/soc/intel/tigerlake/fsp_params.c 1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/39710/6
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39710 )
Change subject: soc/intel/tigerlake: unlock RTC memory ......................................................................
Patch Set 6: Code-Review+1
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39710 )
Change subject: soc/intel/tigerlake: unlock RTC memory ......................................................................
Patch Set 6: Code-Review+2
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39710 )
Change subject: soc/intel/tigerlake: unlock RTC memory ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39710/6/src/soc/intel/tigerlake/fsp... File src/soc/intel/tigerlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/39710/6/src/soc/intel/tigerlake/fsp... PS6, Line 112: params->RtcMemoryLock = 0; On other Intel platforms, we have followed the model of checking get_lockdown_config() before setting RtcMemoryLock, PchLockDownBiosLock and other locks. Any reason TGL isn't following the same?
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39710 )
Change subject: soc/intel/tigerlake: unlock RTC memory ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39710/6/src/soc/intel/tigerlake/fsp... File src/soc/intel/tigerlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/39710/6/src/soc/intel/tigerlake/fsp... PS6, Line 112: params->RtcMemoryLock = 0;
On other Intel platforms, we have followed the model of checking get_lockdown_config() before settin […]
Current code is same as ICL and JSL and we'll check CHIPSET_LOCKDOWN_COREBOOT which is mentioend in b:151161585. For other Lockdown, we're reviewing and update it with different patch and update info in b:151161585.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39710 )
Change subject: soc/intel/tigerlake: unlock RTC memory ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39710/6/src/soc/intel/tigerlake/fsp... File src/soc/intel/tigerlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/39710/6/src/soc/intel/tigerlake/fsp... PS6, Line 112: params->RtcMemoryLock = 0;
Current code is same as ICL and JSL and we'll check CHIPSET_LOCKDOWN_COREBOOT which is mentioend in […]
All lockdown configs should just be handled together. Both ICL and JSL need to be updated as well. I would recommend syncing this with what is done on CNL.
Hello build bot (Jenkins), Shaunak Saha, Furquan Shaikh, Francois Toguo Fotso, Caveh Jalali, Nick Vaccaro, Srinidhi N Kaushik, Raj Astekar, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39710
to look at the new patch set (#7).
Change subject: soc/intel/tigerlake: Implement CHIPSET_LOCKDOWN ......................................................................
soc/intel/tigerlake: Implement CHIPSET_LOCKDOWN
BUG=b:153108724 BRANCH=none TEST=build and boot ripto/volteer and check FSP logs to lockdown parameters
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: I63cec8a718285f424914e426d0399ed821588dfd --- M src/soc/intel/tigerlake/fsp_params.c 1 file changed, 12 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/39710/7
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39710 )
Change subject: soc/intel/tigerlake: Implement CHIPSET_LOCKDOWN ......................................................................
Patch Set 7:
(3 comments)
https://review.coreboot.org/c/coreboot/+/39710/7/src/soc/intel/tigerlake/fsp... File src/soc/intel/tigerlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/39710/7/src/soc/intel/tigerlake/fsp... PS7, Line 119: //params->PchLockDownBiosInterface = 1; code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/39710/7/src/soc/intel/tigerlake/fsp... PS7, Line 120: params->RtcMemoryLock = 1; code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/39710/7/src/soc/intel/tigerlake/fsp... PS7, Line 120: params->RtcMemoryLock = 1; please, no spaces at the start of a line
Hello build bot (Jenkins), Shaunak Saha, Furquan Shaikh, Francois Toguo Fotso, Caveh Jalali, Nick Vaccaro, Srinidhi N Kaushik, Raj Astekar, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39710
to look at the new patch set (#8).
Change subject: soc/intel/tigerlake: Implement CHIPSET_LOCKDOWN ......................................................................
soc/intel/tigerlake: Implement CHIPSET_LOCKDOWN
BUG=b:151161585 BRANCH=none TEST=build and boot ripto/volteer and check FSP logs to lockdown parameters
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: I63cec8a718285f424914e426d0399ed821588dfd --- M src/soc/intel/tigerlake/fsp_params.c 1 file changed, 12 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/39710/8
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39710 )
Change subject: soc/intel/tigerlake: Implement CHIPSET_LOCKDOWN ......................................................................
Patch Set 8:
(4 comments)
https://review.coreboot.org/c/coreboot/+/39710/8/src/soc/intel/tigerlake/fsp... File src/soc/intel/tigerlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/39710/8/src/soc/intel/tigerlake/fsp... PS8, Line 119: params->PchLockDownBiosInterface = 1; code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/39710/8/src/soc/intel/tigerlake/fsp... PS8, Line 119: params->PchLockDownBiosInterface = 1; please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/39710/8/src/soc/intel/tigerlake/fsp... PS8, Line 120: params->RtcMemoryLock = 1; code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/39710/8/src/soc/intel/tigerlake/fsp... PS8, Line 120: params->RtcMemoryLock = 1; please, no spaces at the start of a line
Hello build bot (Jenkins), Shaunak Saha, Furquan Shaikh, Francois Toguo Fotso, Caveh Jalali, Nick Vaccaro, Srinidhi N Kaushik, Raj Astekar, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39710
to look at the new patch set (#9).
Change subject: soc/intel/tigerlake: Implement CHIPSET_LOCKDOWN ......................................................................
soc/intel/tigerlake: Implement CHIPSET_LOCKDOWN
BUG=b:151161585 BRANCH=none TEST=build and boot ripto/volteer and check FSP logs to lockdown parameters
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: I63cec8a718285f424914e426d0399ed821588dfd --- M src/soc/intel/tigerlake/fsp_params.c 1 file changed, 14 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/39710/9
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39710 )
Change subject: soc/intel/tigerlake: Implement CHIPSET_LOCKDOWN ......................................................................
Patch Set 9:
(4 comments)
https://review.coreboot.org/c/coreboot/+/39710/9/src/soc/intel/tigerlake/fsp... File src/soc/intel/tigerlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/39710/9/src/soc/intel/tigerlake/fsp... PS9, Line 120: params->PchLockDownBiosInterface = 1; code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/39710/9/src/soc/intel/tigerlake/fsp... PS9, Line 120: params->PchLockDownBiosInterface = 1; please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/39710/9/src/soc/intel/tigerlake/fsp... PS9, Line 122: params->RtcMemoryLock = 1; code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/39710/9/src/soc/intel/tigerlake/fsp... PS9, Line 122: params->RtcMemoryLock = 1; please, no spaces at the start of a line
Hello build bot (Jenkins), Shaunak Saha, Furquan Shaikh, Francois Toguo Fotso, Caveh Jalali, Nick Vaccaro, Srinidhi N Kaushik, Raj Astekar, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39710
to look at the new patch set (#10).
Change subject: soc/intel/tigerlake: Implement CHIPSET_LOCKDOWN ......................................................................
soc/intel/tigerlake: Implement CHIPSET_LOCKDOWN
BUG=b:151161585 BRANCH=none TEST=build and boot ripto/volteer and check FSP logs to lockdown parameters
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: I63cec8a718285f424914e426d0399ed821588dfd --- M src/soc/intel/tigerlake/fsp_params.c 1 file changed, 14 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/39710/10
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39710 )
Change subject: soc/intel/tigerlake: Implement CHIPSET_LOCKDOWN ......................................................................
Patch Set 10:
(4 comments)
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39710/9/src/soc/intel/tigerlake/fsp... File src/soc/intel/tigerlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/39710/9/src/soc/intel/tigerlake/fsp... PS9, Line 120: params->PchLockDownBiosInterface = 1;
code indent should use tabs where possible
Ack
https://review.coreboot.org/c/coreboot/+/39710/9/src/soc/intel/tigerlake/fsp... PS9, Line 120: params->PchLockDownBiosInterface = 1;
please, no spaces at the start of a line
Ack
https://review.coreboot.org/c/coreboot/+/39710/9/src/soc/intel/tigerlake/fsp... PS9, Line 122: params->RtcMemoryLock = 1;
please, no spaces at the start of a line
Ack
https://review.coreboot.org/c/coreboot/+/39710/9/src/soc/intel/tigerlake/fsp... PS9, Line 122: params->RtcMemoryLock = 1;
code indent should use tabs where possible
Ack
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39710 )
Change subject: soc/intel/tigerlake: Implement CHIPSET_LOCKDOWN ......................................................................
Patch Set 10:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39710/6/src/soc/intel/tigerlake/fsp... File src/soc/intel/tigerlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/39710/6/src/soc/intel/tigerlake/fsp... PS6, Line 112: params->RtcMemoryLock = 0;
All lockdown configs should just be handled together. Both ICL and JSL need to be updated as well. […]
Done and following up UPDs open up for LOCKDOWN
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39710 )
Change subject: soc/intel/tigerlake: Implement CHIPSET_LOCKDOWN ......................................................................
Patch Set 10: Code-Review+1
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39710 )
Change subject: soc/intel/tigerlake: Implement CHIPSET_LOCKDOWN ......................................................................
Patch Set 10:
Following up below UPDs opened PchLockDownGlobalSmi PchLockDownBiosInterface PchUnlockGpioPads
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39710 )
Change subject: soc/intel/tigerlake: Implement CHIPSET_LOCKDOWN ......................................................................
Patch Set 10:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39710/6/src/soc/intel/tigerlake/fsp... File src/soc/intel/tigerlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/39710/6/src/soc/intel/tigerlake/fsp... PS6, Line 112: params->RtcMemoryLock = 0;
Done and following up UPDs open up for LOCKDOWN
Where? Is there a bug for opening up UPDs?
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39710 )
Change subject: soc/intel/tigerlake: Implement CHIPSET_LOCKDOWN ......................................................................
Patch Set 10: Code-Review+1
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39710 )
Change subject: soc/intel/tigerlake: Implement CHIPSET_LOCKDOWN ......................................................................
Patch Set 10: Code-Review+1
(2 comments)
https://review.coreboot.org/c/coreboot/+/39710/10//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39710/10//COMMIT_MSG@11 PS10, Line 11: to for?
https://review.coreboot.org/c/coreboot/+/39710/10/src/soc/intel/tigerlake/fs... File src/soc/intel/tigerlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/39710/10/src/soc/intel/tigerlake/fs... PS10, Line 116: PchUnlockGpioPads Unrelated, it is very confusing to have *Unlock* here and not consistently *Lock*.
Hello build bot (Jenkins), Shaunak Saha, Furquan Shaikh, Francois Toguo Fotso, Caveh Jalali, Paul Menzel, Nick Vaccaro, Srinidhi N Kaushik, Raj Astekar, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39710
to look at the new patch set (#11).
Change subject: soc/intel/tigerlake: Implement CHIPSET_LOCKDOWN ......................................................................
soc/intel/tigerlake: Implement CHIPSET_LOCKDOWN
BUG=b:151161585 BRANCH=none TEST=build and boot ripto/volteer and check FSP logs for lockdown parameters
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: I63cec8a718285f424914e426d0399ed821588dfd --- M src/soc/intel/tigerlake/fsp_params.c 1 file changed, 14 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/39710/11
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39710 )
Change subject: soc/intel/tigerlake: Implement CHIPSET_LOCKDOWN ......................................................................
Patch Set 11:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39710/10/src/soc/intel/tigerlake/fs... File src/soc/intel/tigerlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/39710/10/src/soc/intel/tigerlake/fs... PS10, Line 116: PchUnlockGpioPads
Unrelated, it is very confusing to have *Unlock* here and not consistently *Lock*.
Agree but we can't change name as it's FSP UPD variable
Hello build bot (Jenkins), Shaunak Saha, Furquan Shaikh, Francois Toguo Fotso, Caveh Jalali, Paul Menzel, Nick Vaccaro, Srinidhi N Kaushik, Raj Astekar, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39710
to look at the new patch set (#13).
Change subject: soc/intel/tigerlake: Implement CHIPSET_LOCKDOWN ......................................................................
soc/intel/tigerlake: Implement CHIPSET_LOCKDOWN
BUG=b:151161585 BRANCH=none TEST=build and boot ripto/volteer and check FSP logs for lockdown parameters
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: I63cec8a718285f424914e426d0399ed821588dfd --- M src/soc/intel/tigerlake/fsp_params.c 1 file changed, 14 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/39710/13
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39710 )
Change subject: soc/intel/tigerlake: Implement CHIPSET_LOCKDOWN ......................................................................
Patch Set 13: Code-Review+1
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39710 )
Change subject: soc/intel/tigerlake: Implement CHIPSET_LOCKDOWN ......................................................................
Patch Set 13:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39710/10/src/soc/intel/tigerlake/fs... File src/soc/intel/tigerlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/39710/10/src/soc/intel/tigerlake/fs... PS10, Line 116: PchUnlockGpioPads
Agree but we can't change name as it's FSP UPD variable
Done
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39710 )
Change subject: soc/intel/tigerlake: Implement CHIPSET_LOCKDOWN ......................................................................
Patch Set 13:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39710/6/src/soc/intel/tigerlake/fsp... File src/soc/intel/tigerlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/39710/6/src/soc/intel/tigerlake/fsp... PS6, Line 112: params->RtcMemoryLock = 0;
Done and following up UPDs open up for LOCKDOWN […]
https://review.coreboot.org/c/coreboot/+/40023/ has UPDs
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39710 )
Change subject: soc/intel/tigerlake: Implement CHIPSET_LOCKDOWN ......................................................................
Patch Set 13:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39710/10/src/soc/intel/tigerlake/fs... File src/soc/intel/tigerlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/39710/10/src/soc/intel/tigerlake/fs... PS10, Line 113: CHIPSET_LOCKDOWN_COREBOOT Why does the CHIPSET_LOCKDOWN_COREBOOT case appear to unlock everything and the else case lock down everything? Is this meant to toggle the config state?
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39710 )
Change subject: soc/intel/tigerlake: Implement CHIPSET_LOCKDOWN ......................................................................
Patch Set 13:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39710/10/src/soc/intel/tigerlake/fs... File src/soc/intel/tigerlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/39710/10/src/soc/intel/tigerlake/fs... PS10, Line 113: CHIPSET_LOCKDOWN_COREBOOT
Why does the CHIPSET_LOCKDOWN_COREBOOT case appear to unlock everything and the else case lock down […]
The condistion CHIPSET_LOCKDOWN_COREBOOT hear means do not lockdown inside FSP and Coreboot will lockdown. And this is code for providing parameters to FSP. Actual lockdown implementation is in src/soc/intel/common/pch/lockdown/lockdown.c.
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39710 )
Change subject: soc/intel/tigerlake: Implement CHIPSET_LOCKDOWN ......................................................................
Patch Set 13: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39710 )
Change subject: soc/intel/tigerlake: Implement CHIPSET_LOCKDOWN ......................................................................
soc/intel/tigerlake: Implement CHIPSET_LOCKDOWN
BUG=b:151161585 BRANCH=none TEST=build and boot ripto/volteer and check FSP logs for lockdown parameters
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: I63cec8a718285f424914e426d0399ed821588dfd Reviewed-on: https://review.coreboot.org/c/coreboot/+/39710 Reviewed-by: Nick Vaccaro nvaccaro@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/tigerlake/fsp_params.c 1 file changed, 14 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved Wonkyu Kim: Looks good to me, but someone else must approve
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 231399c..78cfb9f 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -9,6 +9,7 @@ #include <fsp/util.h> #include <intelblocks/lpss.h> #include <intelblocks/xdci.h> +#include <intelpch/lockdown.h> #include <soc/gpio_soc_defs.h> #include <soc/intel/common/vbt.h> #include <soc/pci_devs.h> @@ -97,6 +98,19 @@ for (i = 0; i < 8; i++) params->IomTypeCPortPadCfg[i] = 0x09000000;
+ /* Chipset Lockdown */ + if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT) { + params->PchLockDownGlobalSmi = 0; + params->PchLockDownBiosInterface = 0; + params->PchUnlockGpioPads = 1; + params->RtcMemoryLock = 0; + } else { + params->PchLockDownGlobalSmi = 1; + params->PchLockDownBiosInterface = 1; + params->PchUnlockGpioPads = 0; + params->RtcMemoryLock = 1; + } + /* USB */ for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { params->PortUsb20Enable[i] = config->usb2_ports[i].enable;
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build bot (Jenkins) (Code Review) -
Furquan Shaikh (Code Review)
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Nick Vaccaro (Code Review)
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Patrick Georgi (Code Review)
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Paul Menzel (Code Review)
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Srinidhi N Kaushik (Code Review)
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Wonkyu Kim (Code Review)