Change in coreboot[master]: soc/intel/common/block/lpc: Move common LPC function into block/lpc
Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45787 )
Change subject: soc/intel/common/block/lpc: Move common LPC function into block/lpc ......................................................................
soc/intel/common/block/lpc: Move common LPC function into block/lpc
This patch moves 3 common LPC functions into common block code.
Change-Id: I2a6afc1da50c8ee5bccda7f5671b516dc31fe023 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/common/block/include/intelblocks/lpc_lib.h M src/soc/intel/common/block/lpc/lpc_lib.c 2 files changed, 117 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/45787/1
diff --git a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h index ff4ba1a..65e2c0a 100644 --- a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h +++ b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h @@ -107,5 +107,15 @@ /* Add resource into LPC PCI device space */ void pch_lpc_add_new_resource(struct device *dev, uint8_t offset, uintptr_t base, size_t size, unsigned long flags); +/* Enable PCH IOAPIC */ +void lpc_pch_enable_ioapic(void); +/* Retrieve and setup PCH LPC interrupt routing. */ +void lpc_pch_pirq_init(void); +/* + * LPC MISC programming + * 1. Setup NMI on errors, disable SERR + * 2. Disable NMI sources + */ +void lpc_pch_misc_init(void);
#endif /* _SOC_COMMON_BLOCK_LPC_LIB_H_ */ diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c index ff44cc1..538a81e 100644 --- a/src/soc/intel/common/block/lpc/lpc_lib.c +++ b/src/soc/intel/common/block/lpc/lpc_lib.c @@ -2,13 +2,16 @@
#define __SIMPLE_DEVICE__
+#include <arch/ioapic.h> #include <assert.h> #include <console/console.h> #include <device/pci.h> #include <device/pci_ops.h> +#include <intelblocks/itss.h> #include <intelblocks/lpc_lib.h> #include <lib.h> #include "lpc_def.h" +#include <soc/irq.h> #include <soc/pci_devs.h>
uint16_t lpc_enable_fixed_io_ranges(uint16_t io_enables) @@ -292,3 +295,107 @@ const uint8_t pcctl = pci_read_config8(PCH_DEV_LPC, LPC_PCCTL); pci_write_config8(PCH_DEV_LPC, LPC_PCCTL, pcctl & ~LPC_PCCTL_CLKRUN_EN); } + +/* Enable PCH IOAPIC */ +void lpc_pch_enable_ioapic(void) +{ + uint32_t reg32; + /* PCH-LP has 120 redirection entries */ + const int redir_entries = 120; + + set_ioapic_id((void *)IO_APIC_ADDR, 0x02); + + /* affirm full set of redirection table entries ("write once") */ + reg32 = io_apic_read((void *)IO_APIC_ADDR, 0x01); + + reg32 &= ~0x00ff0000; + reg32 |= (redir_entries - 1) << 16; + + io_apic_write((void *)IO_APIC_ADDR, 0x01, reg32); + + /* + * Select Boot Configuration register (0x03) and + * use Processor System Bus (0x01) to deliver interrupts. + */ + io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01); +} + +/* + * PIRQ[n]_ROUT[3:0] - PIRQ Routing Control + * 0x00 - 0000 = Reserved + * 0x01 - 0001 = Reserved + * 0x02 - 0010 = Reserved + * 0x03 - 0011 = IRQ3 + * 0x04 - 0100 = IRQ4 + * 0x05 - 0101 = IRQ5 + * 0x06 - 0110 = IRQ6 + * 0x07 - 0111 = IRQ7 + * 0x08 - 1000 = Reserved + * 0x09 - 1001 = IRQ9 + * 0x0A - 1010 = IRQ10 + * 0x0B - 1011 = IRQ11 + * 0x0C - 1100 = IRQ12 + * 0x0D - 1101 = Reserved + * 0x0E - 1110 = IRQ14 + * 0x0F - 1111 = IRQ15 + * PIRQ[n]_ROUT[7] - PIRQ Routing Control + * 0x80 - The PIRQ is not routed. + */ +void lpc_pch_pirq_init(void) +{ + const struct device *irq_dev; + uint8_t pch_interrupt_routing[MAX_PXRC_CONFIG]; + + pch_interrupt_routing[0] = PCH_IRQ11; + pch_interrupt_routing[1] = PCH_IRQ10; + pch_interrupt_routing[2] = PCH_IRQ11; + pch_interrupt_routing[3] = PCH_IRQ11; + pch_interrupt_routing[4] = PCH_IRQ11; + pch_interrupt_routing[5] = PCH_IRQ11; + pch_interrupt_routing[6] = PCH_IRQ11; + pch_interrupt_routing[7] = PCH_IRQ11; + + itss_irq_init(pch_interrupt_routing); + + for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { + uint8_t int_pin = 0, int_line = 0; + + if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) + continue; + + int_pin = pci_read_config8(PCI_BDF(irq_dev), PCI_INTERRUPT_PIN); + + switch (int_pin) { + case 1: /* INTA# */ + int_line = PCH_IRQ11; + break; + case 2: /* INTB# */ + int_line = PCH_IRQ10; + break; + case 3: /* INTC# */ + int_line = PCH_IRQ11; + break; + case 4: /* INTD# */ + int_line = PCH_IRQ11; + break; + } + + if (!int_line) + continue; + + pci_write_config8(PCI_BDF(irq_dev), PCI_INTERRUPT_LINE, int_line); + } +} + +/* LPC MISC programming */ +void lpc_pch_misc_init(void) +{ + uint8_t reg8; + + /* Setup NMI on errors, disable SERR */ + reg8 = (inb(0x61)) & 0xf0; + outb((reg8 | (1 << 2)), 0x61); + + /* Disable NMI sources */ + outb((1 << 7), 0x70); +}
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45787
to look at the new patch set (#4).
Change subject: soc/intel/common/block/lpc: Move common LPC function into block/lpc ......................................................................
soc/intel/common/block/lpc: Move common LPC function into block/lpc
This patch moves 3 common LPC functions into common block code.
Change-Id: I2a6afc1da50c8ee5bccda7f5671b516dc31fe023 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/common/block/include/intelblocks/lpc_lib.h M src/soc/intel/common/block/lpc/lpc_lib.c 2 files changed, 117 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/45787/4
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45787
to look at the new patch set (#5).
Change subject: soc/intel/common/block/lpc: Move common LPC function into block/lpc ......................................................................
soc/intel/common/block/lpc: Move common LPC function into block/lpc
This patch moves 3 common LPC functions into common block code.
Change-Id: I2a6afc1da50c8ee5bccda7f5671b516dc31fe023 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/common/block/include/intelblocks/lpc_lib.h M src/soc/intel/common/block/lpc/lpc_lib.c 2 files changed, 117 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/45787/5
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45787 )
Change subject: soc/intel/common/block/lpc: Move common LPC function into block/lpc ......................................................................
Patch Set 5: Code-Review+2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45787 )
Change subject: soc/intel/common/block/lpc: Move common LPC function into block/lpc ......................................................................
Patch Set 5: Code-Review+1
See comments on CB:45789
Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45787
to look at the new patch set (#6).
Change subject: soc/intel: Move pch_enable_ioapic() to common code ......................................................................
soc/intel: Move pch_enable_ioapic() to common code
List of changes: 1. Moves lpc_pch_enable_ioapic() common LPC functions into common block code. 2. Removes redundant LPC functions from SoC directory and refer from block/lpc directory.
TEST=Able to build and boot hatch and tglrvp platform without seeing any functional impact.
Change-Id: I2a6afc1da50c8ee5bccda7f5671b516dc31fe023 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/cannonlake/lpc.c M src/soc/intel/common/block/include/intelblocks/lpc_lib.h M src/soc/intel/common/block/lpc/lpc_lib.c M src/soc/intel/elkhartlake/espi.c M src/soc/intel/icelake/espi.c M src/soc/intel/jasperlake/espi.c M src/soc/intel/skylake/lpc.c M src/soc/intel/tigerlake/espi.c M src/soc/intel/xeon_sp/cpx/chip.c 9 files changed, 35 insertions(+), 161 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/45787/6
Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45787
to look at the new patch set (#7).
Change subject: soc/intel: Move pch_enable_ioapic() to common code ......................................................................
soc/intel: Move pch_enable_ioapic() to common code
List of changes: 1. Rename pch_enable_ioapic() as lpc_pch_enable_ioapic() and move into common block code. 2. Removes redundant LPC functions from SoC directory and refer from block/lpc directory.
TEST=Able to build and boot hatch and tglrvp platform without seeing any functional impact.
Change-Id: I2a6afc1da50c8ee5bccda7f5671b516dc31fe023 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/cannonlake/lpc.c M src/soc/intel/common/block/include/intelblocks/lpc_lib.h M src/soc/intel/common/block/lpc/lpc_lib.c M src/soc/intel/elkhartlake/espi.c M src/soc/intel/icelake/espi.c M src/soc/intel/jasperlake/espi.c M src/soc/intel/skylake/lpc.c M src/soc/intel/tigerlake/espi.c M src/soc/intel/xeon_sp/cpx/chip.c 9 files changed, 35 insertions(+), 161 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/45787/7
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45787 )
Change subject: soc/intel: Move pch_enable_ioapic() to common code ......................................................................
Patch Set 6:
Patch Set 5: Code-Review+1
See comments on CB:45789
Yes Angel, i like the idea, and respin the patchsets accordingly
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45787 )
Change subject: soc/intel: Move pch_enable_ioapic() to common code ......................................................................
Patch Set 7:
Angel, Tim, if you can revisit this patch trend ?
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45787 )
Change subject: soc/intel: Move pch_enable_ioapic() to common code ......................................................................
Patch Set 7: Code-Review+2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45787 )
Change subject: soc/intel: Move pch_enable_ioapic() to common code ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45787/7//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45787/7//COMMIT_MSG@12 PS7, Line 12: Removes nit: Remove
Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45787
to look at the new patch set (#8).
Change subject: soc/intel: Move pch_enable_ioapic() to common code ......................................................................
soc/intel: Move pch_enable_ioapic() to common code
List of changes: 1. Rename pch_enable_ioapic() as lpc_pch_enable_ioapic() and move into common block code. 2. Remove redundant LPC functions from SoC directory and refer from block/lpc directory.
TEST=Able to build and boot hatch and tglrvp platform without seeing any functional impact.
Change-Id: I2a6afc1da50c8ee5bccda7f5671b516dc31fe023 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/cannonlake/lpc.c M src/soc/intel/common/block/include/intelblocks/lpc_lib.h M src/soc/intel/common/block/lpc/lpc_lib.c M src/soc/intel/elkhartlake/espi.c M src/soc/intel/icelake/espi.c M src/soc/intel/jasperlake/espi.c M src/soc/intel/skylake/lpc.c M src/soc/intel/tigerlake/espi.c M src/soc/intel/xeon_sp/cpx/chip.c 9 files changed, 35 insertions(+), 161 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/45787/8
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45787 )
Change subject: soc/intel: Move pch_enable_ioapic() to common code ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45787/7//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45787/7//COMMIT_MSG@12 PS7, Line 12: Removes
nit: Remove
Ack
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45787 )
Change subject: soc/intel: Move pch_enable_ioapic() to common code ......................................................................
Patch Set 8:
Patch Set 7:
Angel, Tim, if you can revisit this patch trend ?
Rebase took those vote again 😭
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45787 )
Change subject: soc/intel: Move pch_enable_ioapic() to common code ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45787/8/src/soc/intel/common/block/... File src/soc/intel/common/block/lpc/lpc_lib.c:
https://review.coreboot.org/c/coreboot/+/45787/8/src/soc/intel/common/block/... PS8, Line 298: lpc_pch_enable_ioapic Why does this belong in the LPC driver?
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45787 )
Change subject: soc/intel: Move pch_enable_ioapic() to common code ......................................................................
Patch Set 8: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/45787/8/src/soc/intel/common/block/... File src/soc/intel/common/block/lpc/lpc_lib.c:
https://review.coreboot.org/c/coreboot/+/45787/8/src/soc/intel/common/block/... PS8, Line 298: lpc_pch_enable_ioapic
Why does this belong in the LPC driver?
Good question. I'm not sure where the IO APIC is located but I'd say it's more likely to be in the SA. However, even ye olde ICH7 says something about IOAPIC in southbridge code.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45787 )
Change subject: soc/intel: Move pch_enable_ioapic() to common code ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45787/8/src/soc/intel/common/block/... File src/soc/intel/common/block/lpc/lpc_lib.c:
https://review.coreboot.org/c/coreboot/+/45787/8/src/soc/intel/common/block/... PS8, Line 298: lpc_pch_enable_ioapic
Good question. […]
its due to pch related code that's why existed since BDW https://github.com/coreboot/coreboot/blob/master/src/soc/intel/broadwell/lpc...
ideally we should have irq.c to keep such code which doesn't existed today. Do you suggest to create something like that ?
Right now all PCH code which can't categories into IP specific is here along with LPC PCI code
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45787 )
Change subject: soc/intel: Move pch_enable_ioapic() to common code ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45787/8/src/soc/intel/common/block/... File src/soc/intel/common/block/lpc/lpc_lib.c:
https://review.coreboot.org/c/coreboot/+/45787/8/src/soc/intel/common/block/... PS8, Line 298: lpc_pch_enable_ioapic
its due to pch related code that's why existed since BDW https://github. […]
Another case of "it's always been done that way". It doesn't necessarily make it right though. `ioapic.c` could also work. Also just rename to `pch_ioapic_enable()` ? It does seem to live in the PCH/ICH/southbridge, as the default IOAPIC addresses decode to DMI.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45787 )
Change subject: soc/intel: Move pch_enable_ioapic() to common code ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45787/8/src/soc/intel/common/block/... File src/soc/intel/common/block/lpc/lpc_lib.c:
https://review.coreboot.org/c/coreboot/+/45787/8/src/soc/intel/common/block/... PS8, Line 298: lpc_pch_enable_ioapic
Another case of "it's always been done that way". It doesn't necessarily make it right though. […]
Yes Tim, i have said irq.c because of ioapic and legacy IRQ as well https://review.coreboot.org/c/coreboot/+/45809/2
@Furquan, do you like to add this into common\pch as irq code block. please share your thought, i really wish to complete ramstage upstream by this week if possible :) looking at the timeline i have in hand 😞
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45787 )
Change subject: soc/intel: Move pch_enable_ioapic() to common code ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45787/8/src/soc/intel/common/block/... File src/soc/intel/common/block/lpc/lpc_lib.c:
https://review.coreboot.org/c/coreboot/+/45787/8/src/soc/intel/common/block/... PS8, Line 298: lpc_pch_enable_ioapic
Yes Tim, i have said irq.c because of ioapic and legacy IRQ as well https://review.coreboot. […]
IMHO, if you could please drop the `lpc_` prefix, I'm fine with this change. Or if there's a name clash with something else, just put a comment "TODO: This isn't really part of LPC"
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45787 )
Change subject: soc/intel: Move pch_enable_ioapic() to common code ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45787/8/src/soc/intel/common/block/... File src/soc/intel/common/block/lpc/lpc_lib.c:
https://review.coreboot.org/c/coreboot/+/45787/8/src/soc/intel/common/block/... PS8, Line 298: lpc_pch_enable_ioapic
IMHO, if you could please drop the `lpc_` prefix, I'm fine with this change. […]
Reason: I'd rather rename this myself later than continue having multiple copies of this code.
Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45787
to look at the new patch set (#9).
Change subject: soc/intel: Move pch_enable_ioapic() to common code ......................................................................
soc/intel: Move pch_enable_ioapic() to common code
List of changes: 1. Move pch_enable_ioapic() into common block code. 2. Remove redundant LPC functions from SoC directory and refer from block/lpc directory.
TEST=Able to build and boot hatch and tglrvp platform without seeing any functional impact.
Change-Id: I2a6afc1da50c8ee5bccda7f5671b516dc31fe023 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/cannonlake/lpc.c M src/soc/intel/common/block/include/intelblocks/lpc_lib.h M src/soc/intel/common/block/lpc/lpc_lib.c M src/soc/intel/elkhartlake/espi.c M src/soc/intel/icelake/espi.c M src/soc/intel/jasperlake/espi.c M src/soc/intel/skylake/lpc.c M src/soc/intel/tigerlake/espi.c M src/soc/intel/xeon_sp/cpx/chip.c 9 files changed, 35 insertions(+), 161 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/45787/9
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45787 )
Change subject: soc/intel: Move pch_enable_ioapic() to common code ......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45787/8/src/soc/intel/common/block/... File src/soc/intel/common/block/lpc/lpc_lib.c:
https://review.coreboot.org/c/coreboot/+/45787/8/src/soc/intel/common/block/... PS8, Line 298: lpc_pch_enable_ioapic
Reason: I'd rather rename this myself later than continue having multiple copies of this code.
Ack
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45787 )
Change subject: soc/intel: Move pch_enable_ioapic() to common code ......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45787/8/src/soc/intel/common/block/... File src/soc/intel/common/block/lpc/lpc_lib.c:
https://review.coreboot.org/c/coreboot/+/45787/8/src/soc/intel/common/block/... PS8, Line 298: lpc_pch_enable_ioapic
Ack
Angel, i have removed "lpc_" prefix, later if you could find a better place for this code, please feel free to move it. 😊
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45787 )
Change subject: soc/intel: Move pch_enable_ioapic() to common code ......................................................................
Patch Set 9: Code-Review+2
Thanks!
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45787 )
Change subject: soc/intel: Move pch_enable_ioapic() to common code ......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45787/8/src/soc/intel/common/block/... File src/soc/intel/common/block/lpc/lpc_lib.c:
https://review.coreboot.org/c/coreboot/+/45787/8/src/soc/intel/common/block/... PS8, Line 298: lpc_pch_enable_ioapic
@Furquan, do you like to add this into common\pch as irq code block.
I think we can continue with this, but I would like to revisit this later.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45787 )
Change subject: soc/intel: Move pch_enable_ioapic() to common code ......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45787/8/src/soc/intel/common/block/... File src/soc/intel/common/block/lpc/lpc_lib.c:
https://review.coreboot.org/c/coreboot/+/45787/8/src/soc/intel/common/block/... PS8, Line 298: lpc_pch_enable_ioapic
@Furquan, do you like to add this into common\pch as irq code block. […]
Sure Furquan
Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45787
to look at the new patch set (#10).
Change subject: soc/intel: Move pch_enable_ioapic() to common code ......................................................................
soc/intel: Move pch_enable_ioapic() to common code
List of changes: 1. Move pch_enable_ioapic() into common block code. 2. Remove redundant LPC functions from SoC directory and refer from block/lpc directory.
TEST=Able to build and boot hatch and tglrvp platform without seeing any functional impact.
Change-Id: I2a6afc1da50c8ee5bccda7f5671b516dc31fe023 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/cannonlake/lpc.c M src/soc/intel/common/block/include/intelblocks/lpc_lib.h M src/soc/intel/common/block/lpc/lpc_lib.c M src/soc/intel/elkhartlake/espi.c M src/soc/intel/icelake/espi.c M src/soc/intel/jasperlake/espi.c M src/soc/intel/skylake/lpc.c M src/soc/intel/tigerlake/espi.c M src/soc/intel/xeon_sp/cpx/chip.c 9 files changed, 35 insertions(+), 161 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/45787/10
Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45787 )
Change subject: soc/intel: Move pch_enable_ioapic() to common code ......................................................................
soc/intel: Move pch_enable_ioapic() to common code
List of changes: 1. Move pch_enable_ioapic() into common block code. 2. Remove redundant LPC functions from SoC directory and refer from block/lpc directory.
TEST=Able to build and boot hatch and tglrvp platform without seeing any functional impact.
Change-Id: I2a6afc1da50c8ee5bccda7f5671b516dc31fe023 Signed-off-by: Subrata Banik subrata.banik@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/45787 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com --- M src/soc/intel/cannonlake/lpc.c M src/soc/intel/common/block/include/intelblocks/lpc_lib.h M src/soc/intel/common/block/lpc/lpc_lib.c M src/soc/intel/elkhartlake/espi.c M src/soc/intel/icelake/espi.c M src/soc/intel/jasperlake/espi.c M src/soc/intel/skylake/lpc.c M src/soc/intel/tigerlake/espi.c M src/soc/intel/xeon_sp/cpx/chip.c 9 files changed, 35 insertions(+), 161 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/src/soc/intel/cannonlake/lpc.c b/src/soc/intel/cannonlake/lpc.c index 50af9ee..9d36f32 100644 --- a/src/soc/intel/cannonlake/lpc.c +++ b/src/soc/intel/cannonlake/lpc.c @@ -90,28 +90,6 @@ soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]); }
-static void pch_enable_ioapic(const struct device *dev) -{ - u32 reg32; - /* PCH-LP has 120 redirection entries */ - const int redir_entries = 120; - - set_ioapic_id((void *)IO_APIC_ADDR, 0x02); - - /* affirm full set of redirection table entries ("write once") */ - reg32 = io_apic_read((void *)IO_APIC_ADDR, 0x01); - - reg32 &= ~0x00ff0000; - reg32 |= (redir_entries - 1) << 16; - - io_apic_write((void *)IO_APIC_ADDR, 0x01, reg32); - - /* - * Select Boot Configuration register (0x03) and - * use Processor System Bus (0x01) to deliver interrupts. - */ - io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01); -} /* * PIRQ[n]_ROUT[3:0] - PIRQ Routing Control * 0x00 - 0000 = Reserved @@ -207,7 +185,7 @@ lpc_set_serirq_mode(config->serirq_mode);
/* Interrupt configuration */ - pch_enable_ioapic(dev); + pch_enable_ioapic(); soc_pch_pirq_init(dev); setup_i8259(); i8259_configure_irq_trigger(9, 1); diff --git a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h index ff4ba1a..5bbc384 100644 --- a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h +++ b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h @@ -107,5 +107,7 @@ /* Add resource into LPC PCI device space */ void pch_lpc_add_new_resource(struct device *dev, uint8_t offset, uintptr_t base, size_t size, unsigned long flags); +/* Enable PCH IOAPIC */ +void pch_enable_ioapic(void);
#endif /* _SOC_COMMON_BLOCK_LPC_LIB_H_ */ diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c index ff44cc1..87ee110 100644 --- a/src/soc/intel/common/block/lpc/lpc_lib.c +++ b/src/soc/intel/common/block/lpc/lpc_lib.c @@ -2,6 +2,7 @@
#define __SIMPLE_DEVICE__
+#include <arch/ioapic.h> #include <assert.h> #include <console/console.h> #include <device/pci.h> @@ -292,3 +293,27 @@ const uint8_t pcctl = pci_read_config8(PCH_DEV_LPC, LPC_PCCTL); pci_write_config8(PCH_DEV_LPC, LPC_PCCTL, pcctl & ~LPC_PCCTL_CLKRUN_EN); } + +/* Enable PCH IOAPIC */ +void pch_enable_ioapic(void) +{ + uint32_t reg32; + /* PCH-LP has 120 redirection entries */ + const int redir_entries = 120; + + set_ioapic_id((void *)IO_APIC_ADDR, 0x02); + + /* affirm full set of redirection table entries ("write once") */ + reg32 = io_apic_read((void *)IO_APIC_ADDR, 0x01); + + reg32 &= ~0x00ff0000; + reg32 |= (redir_entries - 1) << 16; + + io_apic_write((void *)IO_APIC_ADDR, 0x01, reg32); + + /* + * Select Boot Configuration register (0x03) and + * use Processor System Bus (0x01) to deliver interrupts. + */ + io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01); +} diff --git a/src/soc/intel/elkhartlake/espi.c b/src/soc/intel/elkhartlake/espi.c index 7133997..2412623 100644 --- a/src/soc/intel/elkhartlake/espi.c +++ b/src/soc/intel/elkhartlake/espi.c @@ -64,28 +64,6 @@ soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]); }
-static void pch_enable_ioapic(const struct device *dev) -{ - uint32_t reg32; - /* PCH-LP has 120 redirection entries */ - const int redir_entries = 120; - - set_ioapic_id((void *)IO_APIC_ADDR, 0x02); - - /* affirm full set of redirection table entries ("write once") */ - reg32 = io_apic_read((void *)IO_APIC_ADDR, 0x01); - - reg32 &= ~0x00ff0000; - reg32 |= (redir_entries - 1) << 16; - - io_apic_write((void *)IO_APIC_ADDR, 0x01, reg32); - - /* - * Select Boot Configuration register (0x03) and - * use Processor System Bus (0x01) to deliver interrupts. - */ - io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01); -} /* * PIRQ[n]_ROUT[3:0] - PIRQ Routing Control * 0x00 - 0000 = Reserved @@ -182,7 +160,7 @@ lpc_set_serirq_mode(SERIRQ_QUIET);
/* Interrupt configuration */ - pch_enable_ioapic(dev); + pch_enable_ioapic(); soc_pch_pirq_init(dev); setup_i8259(); i8259_configure_irq_trigger(9, 1); diff --git a/src/soc/intel/icelake/espi.c b/src/soc/intel/icelake/espi.c index 1497c8d..bf5c50d 100644 --- a/src/soc/intel/icelake/espi.c +++ b/src/soc/intel/icelake/espi.c @@ -83,28 +83,6 @@ soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]); }
-static void pch_enable_ioapic(const struct device *dev) -{ - u32 reg32; - /* PCH-LP has 120 redirection entries */ - const int redir_entries = 120; - - set_ioapic_id((void *)IO_APIC_ADDR, 0x02); - - /* affirm full set of redirection table entries ("write once") */ - reg32 = io_apic_read((void *)IO_APIC_ADDR, 0x01); - - reg32 &= ~0x00ff0000; - reg32 |= (redir_entries - 1) << 16; - - io_apic_write((void *)IO_APIC_ADDR, 0x01, reg32); - - /* - * Select Boot Configuration register (0x03) and - * use Processor System Bus (0x01) to deliver interrupts. - */ - io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01); -} /* * PIRQ[n]_ROUT[3:0] - PIRQ Routing Control * 0x00 - 0000 = Reserved @@ -201,7 +179,7 @@ lpc_set_serirq_mode(SERIRQ_QUIET);
/* Interrupt configuration */ - pch_enable_ioapic(dev); + pch_enable_ioapic(); soc_pch_pirq_init(dev); setup_i8259(); i8259_configure_irq_trigger(9, 1); diff --git a/src/soc/intel/jasperlake/espi.c b/src/soc/intel/jasperlake/espi.c index bf82067..24b5057 100644 --- a/src/soc/intel/jasperlake/espi.c +++ b/src/soc/intel/jasperlake/espi.c @@ -65,28 +65,6 @@ soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]); }
-static void pch_enable_ioapic(const struct device *dev) -{ - u32 reg32; - /* PCH-LP has 120 redirection entries */ - const int redir_entries = 120; - - set_ioapic_id((void *)IO_APIC_ADDR, 0x02); - - /* affirm full set of redirection table entries ("write once") */ - reg32 = io_apic_read((void *)IO_APIC_ADDR, 0x01); - - reg32 &= ~0x00ff0000; - reg32 |= (redir_entries - 1) << 16; - - io_apic_write((void *)IO_APIC_ADDR, 0x01, reg32); - - /* - * Select Boot Configuration register (0x03) and - * use Processor System Bus (0x01) to deliver interrupts. - */ - io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01); -} /* * PIRQ[n]_ROUT[3:0] - PIRQ Routing Control * 0x00 - 0000 = Reserved @@ -183,7 +161,7 @@ lpc_set_serirq_mode(SERIRQ_QUIET);
/* Interrupt configuration */ - pch_enable_ioapic(dev); + pch_enable_ioapic(); soc_pch_pirq_init(dev); setup_i8259(); i8259_configure_irq_trigger(9, 1); diff --git a/src/soc/intel/skylake/lpc.c b/src/soc/intel/skylake/lpc.c index 7dc90f0..e514e1a 100644 --- a/src/soc/intel/skylake/lpc.c +++ b/src/soc/intel/skylake/lpc.c @@ -29,29 +29,6 @@ return skl_lpc_fixed_mmio_ranges; }
-static void pch_enable_ioapic(struct device *dev) -{ - u32 reg32; - /* PCH-LP has 120 redirection entries */ - const int redir_entries = 120; - - set_ioapic_id((void *)IO_APIC_ADDR, 0x02); - - /* affirm full set of redirection table entries ("write once") */ - reg32 = io_apic_read((void *)IO_APIC_ADDR, 0x01); - - reg32 &= ~0x00ff0000; - reg32 |= (redir_entries - 1) << 16; - - io_apic_write((void *)IO_APIC_ADDR, 0x01, reg32); - - /* - * Select Boot Configuration register (0x03) and - * use Processor System Bus (0x01) to deliver interrupts. - */ - io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01); -} - void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec) { const config_t *config = config_of(dev); @@ -96,7 +73,7 @@ lpc_set_serirq_mode(config->serirq_mode);
/* Interrupt configuration */ - pch_enable_ioapic(dev); + pch_enable_ioapic(); soc_pch_pirq_init(dev); setup_i8259(); i8259_configure_irq_trigger(9, 1); diff --git a/src/soc/intel/tigerlake/espi.c b/src/soc/intel/tigerlake/espi.c index 513da5a..eb44a6a 100644 --- a/src/soc/intel/tigerlake/espi.c +++ b/src/soc/intel/tigerlake/espi.c @@ -71,28 +71,6 @@ soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]); }
-static void pch_enable_ioapic(const struct device *dev) -{ - u32 reg32; - /* PCH-LP has 120 redirection entries */ - const int redir_entries = 120; - - set_ioapic_id((void *)IO_APIC_ADDR, 0x02); - - /* affirm full set of redirection table entries ("write once") */ - reg32 = io_apic_read((void *)IO_APIC_ADDR, 0x01); - - reg32 &= ~0x00ff0000; - reg32 |= (redir_entries - 1) << 16; - - io_apic_write((void *)IO_APIC_ADDR, 0x01, reg32); - - /* - * Select Boot Configuration register (0x03) and - * use Processor System Bus (0x01) to deliver interrupts. - */ - io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01); -} /* * PIRQ[n]_ROUT[3:0] - PIRQ Routing Control * 0x00 - 0000 = Reserved @@ -189,7 +167,7 @@ lpc_set_serirq_mode(SERIRQ_QUIET);
/* Interrupt configuration */ - pch_enable_ioapic(dev); + pch_enable_ioapic(); soc_pch_pirq_init(dev); setup_i8259(); i8259_configure_irq_trigger(9, 1); diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c index 5ee7f6c..11fe44b 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.c +++ b/src/soc/intel/xeon_sp/cpx/chip.c @@ -6,6 +6,7 @@ #include <cpu/x86/lapic.h> #include <device/pci.h> #include <fsp/api.h> +#include <intelblocks/lpc_lib.h> #include <intelblocks/p2sb.h> #include <post.h> #include <soc/acpi.h> @@ -557,27 +558,6 @@ DEV_FUNC_EXIT(dev); }
-static void pch_enable_ioapic(const struct device *dev) -{ - uint32_t reg32; - - set_ioapic_id((void *)IO_APIC_ADDR, 2); - - /* affirm full set of redirection table entries ("write once") */ - reg32 = io_apic_read((void *)IO_APIC_ADDR, 1); - - reg32 &= ~0x00ff0000; - reg32 |= (C620_IOAPIC_REDIR_ENTRIES - 1) << 16; - - io_apic_write((void *)IO_APIC_ADDR, 1, reg32); - - /* - * Select Boot Configuration register (0x03) and - * use Processor System Bus (0x01) to deliver interrupts. - */ - io_apic_write((void *)IO_APIC_ADDR, 3, 1); -} - struct pci_operations soc_pci_ops = { .set_subsystem = pci_dev_set_subsystem, }; @@ -604,7 +584,7 @@ { printk(BIOS_DEBUG, "coreboot: calling fsp_silicon_init\n"); fsp_silicon_init(false); - pch_enable_ioapic(NULL); + pch_enable_ioapic(); setup_lapic(); p2sb_unhide(); }
-
Angel Pons (Code Review) -
Furquan Shaikh (Code Review)
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Subrata Banik (Code Review)
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Tim Wawrzynczak (Code Review)