[M] Change in coreboot[master]: soc/amd/mendocino: Expand extra 5 DPTC thermal related profiles

[Tim Van Patten (Code Review)]

Attention is currently required from: Jason Glenesk, Raul Rangel, EricKY Cheng, Matt DeVillier, Chris Wang, Fred Reitberger, Karthikeyan Ramasubramanian, Felix Held.

Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68469 )

Change subject: soc/amd/mendocino: Expand extra 5 DPTC thermal related profiles
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Patch Set 8:

(1 comment)

File src/soc/amd/mendocino/chip.h:

https://review.coreboot.org/c/coreboot/+/68469/comment/e11eb512_a05b7ef7 
PS4, Line 77: 	uint32_t sustained_power_limit_mW_B;
            : 	uint32_t fast_ppt_limit_mW_B;
            : 	uint32_t slow_ppt_limit_mW_B;
            : 	uint32_t slow_ppt_time_constant_s_B;
            : 	uint32_t thermctl_limit_degreeC_B;
> Hi Tim, […]

Let's reduce the change to only what's necessary, meaning only the settings that are actually changing between each table.   Changing the values will require a new CL anyway, and we can add new fields then if necessary.