Change in coreboot[master]: vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v2527.

[Srinidhi N Kaushik (Code Review)]

Hello build bot (Jenkins), Furquan Shaikh, Wonkyu Kim, Nick Vaccaro, Ronak Kanabar, Raj Astekar, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/40026

to look at the new patch set (#9).

Change subject: vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v2527.
......................................................................

vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v2527.

Update FSP headers for Tiger Lake platform generated based FSP
version 2527. Which includes below additional UPDs
FSPM:
 - PchTraceHubMode
 - CpuTraceHubMode
 - CpuPcieRpEnableMask
FSPS:
 - D3HotEnable
 - D3ColdEnable
 - RtcMemoryLock
 - PchLockDownGlobalSmi
 - PchLockDownBiosInterface
 - PchUnlockGpioPads
 - CpuMpPpi
 - ThcPort0Assignment
 - ThcPort1Assignment

BUG=b:150357377
BRANCH=none
TEST=build and boot ripto/volteer

Signed-off-by: Srinidhi N Kaushik 
Change-Id: I0cdce28b01f291dbb02a01ded7629e94c77b7e47
---
M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspUpd.h
M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h
M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h
3 files changed, 168 insertions(+), 66 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/40026/9