Change in coreboot[master]: soc/amd/cezanne: Generate PCI routing table - coreboot-gerrit

6 May 2021


      Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held.
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51556 )
Change subject: soc/amd/cezanne: Generate PCI routing table
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Patch Set 5:
(1 comment)
File src/soc/amd/cezanne/pcie_gpp.c:
https://review.coreboot.org/c/coreboot/+/51556/comment/c7327043_7f3792b7 
PS5, Line 68: Enable GNB IO-APIC
...
see CB:52905 which adds that. feel free to take over that one. […]
Yeah, I'll take over it once these patches land. It's not a blocker so I deprioritized it.
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Gerrit-Project: coreboot
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Gerrit-Change-Id: Idb559335435a95e73640e6d7fb224e16e0592326
Gerrit-Change-Number: 51556
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