Philipp Deppenwiese has uploaded this change for review. ( https://review.coreboot.org/29402
Change subject: northbridge/intel/fsp_*: Remove legacy SoCs ......................................................................
northbridge/intel/fsp_*: Remove legacy SoCs
* Remove FSP Sandy/Ivybrige which are unused. * Open Source implementation isn't final but good enough to replace FSP version. * For new ports use NORTHBRIDGE_INTEL_IVYBRIDGE and NORTHBRIDGE_INTEL_SANDYBRIDGE
Change-Id: I7b6bc4bfdd0481c8fe5b2b3d8f8b2eb9aa3c3b9e Signed-off-by: zaolin zaolin.daisuki@gmail.com --- M src/cpu/intel/Makefile.inc D src/cpu/intel/fsp_model_206ax/Kconfig D src/cpu/intel/fsp_model_206ax/Makefile.inc D src/cpu/intel/fsp_model_206ax/acpi.c D src/cpu/intel/fsp_model_206ax/acpi/cpu.asl D src/cpu/intel/fsp_model_206ax/bootblock.c D src/cpu/intel/fsp_model_206ax/chip.h D src/cpu/intel/fsp_model_206ax/finalize.c D src/cpu/intel/fsp_model_206ax/model_206ax.h D src/cpu/intel/fsp_model_206ax/model_206ax_init.c D src/mainboard/intel/cougar_canyon2/Kconfig D src/mainboard/intel/cougar_canyon2/Kconfig.name D src/mainboard/intel/cougar_canyon2/acpi/ec.asl D src/mainboard/intel/cougar_canyon2/acpi/hostbridge_pci_irqs.asl D src/mainboard/intel/cougar_canyon2/acpi/mainboard.asl D src/mainboard/intel/cougar_canyon2/acpi/platform.asl D src/mainboard/intel/cougar_canyon2/acpi/superio.asl D src/mainboard/intel/cougar_canyon2/acpi_tables.c D src/mainboard/intel/cougar_canyon2/board_info.txt D src/mainboard/intel/cougar_canyon2/cmos.layout D src/mainboard/intel/cougar_canyon2/devicetree.cb D src/mainboard/intel/cougar_canyon2/dsdt.asl D src/mainboard/intel/cougar_canyon2/gpio.h D src/mainboard/intel/cougar_canyon2/hda_verb.c D src/mainboard/intel/cougar_canyon2/mainboard.c D src/mainboard/intel/cougar_canyon2/mainboard_smi.c D src/mainboard/intel/cougar_canyon2/romstage.c D src/mainboard/intel/cougar_canyon2/thermal.h D src/mainboard/intel/stargo2/Kconfig D src/mainboard/intel/stargo2/Kconfig.name D src/mainboard/intel/stargo2/acpi/ec.asl D src/mainboard/intel/stargo2/acpi/hostbridge_pci_irqs.asl D src/mainboard/intel/stargo2/acpi/mainboard.asl D src/mainboard/intel/stargo2/acpi/platform.asl D src/mainboard/intel/stargo2/acpi/superio.asl D src/mainboard/intel/stargo2/acpi_tables.c D src/mainboard/intel/stargo2/board_info.txt D src/mainboard/intel/stargo2/cmos.layout D src/mainboard/intel/stargo2/devicetree.cb D src/mainboard/intel/stargo2/dsdt.asl D src/mainboard/intel/stargo2/gpio.h D src/mainboard/intel/stargo2/mainboard.c D src/mainboard/intel/stargo2/mainboard_smi.c D src/mainboard/intel/stargo2/romstage.c D src/mainboard/intel/stargo2/thermal.h D src/northbridge/intel/fsp_sandybridge/Kconfig D src/northbridge/intel/fsp_sandybridge/Makefile.inc D src/northbridge/intel/fsp_sandybridge/acpi.c D src/northbridge/intel/fsp_sandybridge/acpi/hostbridge.asl D src/northbridge/intel/fsp_sandybridge/acpi/sandybridge.asl D src/northbridge/intel/fsp_sandybridge/bootblock.c D src/northbridge/intel/fsp_sandybridge/chip.h D src/northbridge/intel/fsp_sandybridge/early_init.c D src/northbridge/intel/fsp_sandybridge/finalize.c D src/northbridge/intel/fsp_sandybridge/fsp/Kconfig D src/northbridge/intel/fsp_sandybridge/fsp/Makefile.inc D src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c D src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.h D src/northbridge/intel/fsp_sandybridge/gma.c D src/northbridge/intel/fsp_sandybridge/northbridge.c D src/northbridge/intel/fsp_sandybridge/northbridge.h D src/northbridge/intel/fsp_sandybridge/northbridge_pci_devs.h D src/northbridge/intel/fsp_sandybridge/ram_calc.c D src/northbridge/intel/fsp_sandybridge/raminit.c D src/northbridge/intel/fsp_sandybridge/raminit.h D src/northbridge/intel/fsp_sandybridge/report_platform.c M src/vendorcode/intel/Kconfig D src/vendorcode/intel/fsp1_0/ivybridge_bd82x6x/include/fspapi.h D src/vendorcode/intel/fsp1_0/ivybridge_bd82x6x/include/fspffs.h D src/vendorcode/intel/fsp1_0/ivybridge_bd82x6x/include/fspfv.h D src/vendorcode/intel/fsp1_0/ivybridge_bd82x6x/include/fsphob.h D src/vendorcode/intel/fsp1_0/ivybridge_bd82x6x/include/fspinfoheader.h D src/vendorcode/intel/fsp1_0/ivybridge_bd82x6x/include/fspplatform.h D src/vendorcode/intel/fsp1_0/ivybridge_bd82x6x/include/fsptypes.h D src/vendorcode/intel/fsp1_0/ivybridge_bd82x6x/include/mem_config.h D src/vendorcode/intel/fsp1_0/ivybridge_bd82x6x/include/peifsp.h D src/vendorcode/intel/fsp1_0/ivybridge_bd82x6x/srx/fsphob.c D src/vendorcode/intel/fsp1_0/ivybridge_i89xx/include/fsp_vpd.h D src/vendorcode/intel/fsp1_0/ivybridge_i89xx/include/fspapi.h D src/vendorcode/intel/fsp1_0/ivybridge_i89xx/include/fspffs.h D src/vendorcode/intel/fsp1_0/ivybridge_i89xx/include/fspfv.h D src/vendorcode/intel/fsp1_0/ivybridge_i89xx/include/fsphob.h D src/vendorcode/intel/fsp1_0/ivybridge_i89xx/include/fspinfoheader.h D src/vendorcode/intel/fsp1_0/ivybridge_i89xx/include/fspplatform.h D src/vendorcode/intel/fsp1_0/ivybridge_i89xx/include/fsptypes.h D src/vendorcode/intel/fsp1_0/ivybridge_i89xx/include/mem_config.h D src/vendorcode/intel/fsp1_0/ivybridge_i89xx/include/peifsp.h D src/vendorcode/intel/fsp1_0/ivybridge_i89xx/srx/fsphob.c 88 files changed, 0 insertions(+), 9,572 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/29402/1
-
Philipp Deppenwiese (Code Review)