Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45300 )
Change subject: soc/amd/picasso/chip: fix typo in acp_pme_enable ......................................................................
soc/amd/picasso/chip: fix typo in acp_pme_enable
That devicetree setting is about the Audio Co-Processor and not ACPI.
BRANCH=zork
Change-Id: I7f376371ee094392d4434340c77f0fc8d0d8e4e1 Signed-off-by: Felix Held felix-coreboot@felixheld.de --- M src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb M src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb M src/mainboard/google/zork/variants/baseboard/ramstage_common.c M src/soc/amd/picasso/acp.c M src/soc/amd/picasso/chip.h 5 files changed, 5 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/45300/1
diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb index 42219d7..a0f6636 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb @@ -8,7 +8,7 @@
register "acp_pin_cfg" = "I2S_PINS_I2S_TDM" register "acp_i2s_wake_enable" = "0" - register "acpi_pme_enable" = "0" + register "acp_pme_enable" = "0"
# Start : OPN Performance Configuration # (Configuratin that is common for all variants) diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb index 1620643..1694519 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb @@ -8,7 +8,7 @@
register "acp_pin_cfg" = "I2S_PINS_I2S_TDM" register "acp_i2s_wake_enable" = "0" - register "acpi_pme_enable" = "0" + register "acp_pme_enable" = "0"
# Start : OPN Performance Configuration # (Configuratin that is common for all variants) diff --git a/src/mainboard/google/zork/variants/baseboard/ramstage_common.c b/src/mainboard/google/zork/variants/baseboard/ramstage_common.c index 664f659..c2a0294 100644 --- a/src/mainboard/google/zork/variants/baseboard/ramstage_common.c +++ b/src/mainboard/google/zork/variants/baseboard/ramstage_common.c @@ -71,7 +71,7 @@ */ soc_cfg = config_of_soc(); soc_cfg->acp_i2s_wake_enable = 1; - soc_cfg->acpi_pme_enable = 1; + soc_cfg->acp_pme_enable = 1; }
static void update_dmic_gpio(void) diff --git a/src/soc/amd/picasso/acp.c b/src/soc/amd/picasso/acp.c index 8e6f4cf..9ee29551 100644 --- a/src/soc/amd/picasso/acp.c +++ b/src/soc/amd/picasso/acp.c @@ -45,7 +45,7 @@
/* Enable ACP_PME_EN and ACP_I2S_WAKE_EN for I2S_WAKE event */ acp_update32(bar, ACP_I2S_WAKE_EN, WAKE_EN_MASK, !!cfg->acp_i2s_wake_enable); - acp_update32(bar, ACP_PME_EN, PME_EN_MASK, !!cfg->acpi_pme_enable); + acp_update32(bar, ACP_PME_EN, PME_EN_MASK, !!cfg->acp_pme_enable);
if (cfg->acp_pin_cfg == I2S_PINS_I2S_TDM) sb_clk_output_48Mhz(); /* Internal connection to I2S */ diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index ac1a12c..ad492e0 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -63,7 +63,7 @@ /* Enable ACP I2S wake feature (0 = disable, 1 = enable) */ u8 acp_i2s_wake_enable; /* Enable ACP PME (0 = disable, 1 = enable) */ - u8 acpi_pme_enable; + u8 acp_pme_enable;
/** * IRQ 0 - 15 have a default trigger of edge and default polarity of high.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45300 )
Change subject: soc/amd/picasso/chip: fix typo in acp_pme_enable ......................................................................
Patch Set 1: Code-Review+2
Thanks for fixing this!
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45300 )
Change subject: soc/amd/picasso/chip: fix typo in acp_pme_enable ......................................................................
Patch Set 1: Code-Review+2
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45300 )
Change subject: soc/amd/picasso/chip: fix typo in acp_pme_enable ......................................................................
soc/amd/picasso/chip: fix typo in acp_pme_enable
That devicetree setting is about the Audio Co-Processor and not ACPI.
BRANCH=zork
Change-Id: I7f376371ee094392d4434340c77f0fc8d0d8e4e1 Signed-off-by: Felix Held felix-coreboot@felixheld.de Reviewed-on: https://review.coreboot.org/c/coreboot/+/45300 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Furquan Shaikh furquan@google.com Reviewed-by: Raul Rangel rrangel@chromium.org --- M src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb M src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb M src/mainboard/google/zork/variants/baseboard/ramstage_common.c M src/soc/amd/picasso/acp.c M src/soc/amd/picasso/chip.h 5 files changed, 5 insertions(+), 5 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Raul Rangel: Looks good to me, approved
diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb index 42219d7..a0f6636 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb @@ -8,7 +8,7 @@
register "acp_pin_cfg" = "I2S_PINS_I2S_TDM" register "acp_i2s_wake_enable" = "0" - register "acpi_pme_enable" = "0" + register "acp_pme_enable" = "0"
# Start : OPN Performance Configuration # (Configuratin that is common for all variants) diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb index 1620643..1694519 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb @@ -8,7 +8,7 @@
register "acp_pin_cfg" = "I2S_PINS_I2S_TDM" register "acp_i2s_wake_enable" = "0" - register "acpi_pme_enable" = "0" + register "acp_pme_enable" = "0"
# Start : OPN Performance Configuration # (Configuratin that is common for all variants) diff --git a/src/mainboard/google/zork/variants/baseboard/ramstage_common.c b/src/mainboard/google/zork/variants/baseboard/ramstage_common.c index 664f659..c2a0294 100644 --- a/src/mainboard/google/zork/variants/baseboard/ramstage_common.c +++ b/src/mainboard/google/zork/variants/baseboard/ramstage_common.c @@ -71,7 +71,7 @@ */ soc_cfg = config_of_soc(); soc_cfg->acp_i2s_wake_enable = 1; - soc_cfg->acpi_pme_enable = 1; + soc_cfg->acp_pme_enable = 1; }
static void update_dmic_gpio(void) diff --git a/src/soc/amd/picasso/acp.c b/src/soc/amd/picasso/acp.c index 8e6f4cf..9ee29551 100644 --- a/src/soc/amd/picasso/acp.c +++ b/src/soc/amd/picasso/acp.c @@ -45,7 +45,7 @@
/* Enable ACP_PME_EN and ACP_I2S_WAKE_EN for I2S_WAKE event */ acp_update32(bar, ACP_I2S_WAKE_EN, WAKE_EN_MASK, !!cfg->acp_i2s_wake_enable); - acp_update32(bar, ACP_PME_EN, PME_EN_MASK, !!cfg->acpi_pme_enable); + acp_update32(bar, ACP_PME_EN, PME_EN_MASK, !!cfg->acp_pme_enable);
if (cfg->acp_pin_cfg == I2S_PINS_I2S_TDM) sb_clk_output_48Mhz(); /* Internal connection to I2S */ diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index ac1a12c..ad492e0 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -63,7 +63,7 @@ /* Enable ACP I2S wake feature (0 = disable, 1 = enable) */ u8 acp_i2s_wake_enable; /* Enable ACP PME (0 = disable, 1 = enable) */ - u8 acpi_pme_enable; + u8 acp_pme_enable;
/** * IRQ 0 - 15 have a default trigger of edge and default polarity of high.
-
Felix Held (Code Review) -
Furquan Shaikh (Code Review)
-
Raul Rangel (Code Review)