Change in coreboot[master]: soc/intel/jasperlake: add processor power limits control support
Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41777 )
Change subject: soc/intel/jasperlake: add processor power limits control support ......................................................................
soc/intel/jasperlake: add processor power limits control support
Add processor power limits control support to configure values for jasperlake soc based platforms.
BRANCH=None BUG=None TEST=Built for dedede system
Change-Id: Ib5502b225c1158c1f0729ce799ed0b8101f0233f Signed-off-by: Sumeet R Pawnikar sumeet.r.pawnikar@intel.com --- M src/soc/intel/jasperlake/systemagent.c 1 file changed, 11 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/41777/1
diff --git a/src/soc/intel/jasperlake/systemagent.c b/src/soc/intel/jasperlake/systemagent.c index db56cc0..bdf8fee 100644 --- a/src/soc/intel/jasperlake/systemagent.c +++ b/src/soc/intel/jasperlake/systemagent.c @@ -1,10 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <device/device.h> +#include <delay.h> #include <device/pci.h> #include <device/pci_ops.h> #include <intelblocks/systemagent.h> +#include <intelblocks/power_limit.h> #include <soc/iomap.h> +#include <soc/soc_chip.h> #include <soc/systemagent.h>
/* @@ -54,9 +57,17 @@ */ void soc_systemagent_init(struct device *dev) { + struct soc_power_limits_config *soc_config; + config_t *config; + /* Enable Power Aware Interrupt Routing */ enable_power_aware_intr();
/* Enable BIOS Reset CPL */ enable_bios_reset_cpl(); + + mdelay(1); + config = config_of_soc(); + soc_config = &config->power_limits_config; + set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config); }
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41777 )
Change subject: soc/intel/jasperlake: add processor power limits control support ......................................................................
Patch Set 1: Code-Review+2
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41777 )
Change subject: soc/intel/jasperlake: add processor power limits control support ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/41777/1/src/soc/intel/jasperlake/sy... File src/soc/intel/jasperlake/systemagent.c:
https://review.coreboot.org/c/coreboot/+/41777/1/src/soc/intel/jasperlake/sy... PS1, Line 69: mdelay(1); Can you please add a comment regarding why the delay is required? Does BIOS reset CPL turn on some resources required before setting power limits? Is this requirement captured in a doc?
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41777 )
Change subject: soc/intel/jasperlake: add processor power limits control support ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/41777/1/src/soc/intel/jasperlake/sy... File src/soc/intel/jasperlake/systemagent.c:
https://review.coreboot.org/c/coreboot/+/41777/1/src/soc/intel/jasperlake/sy... PS1, Line 69: mdelay(1);
Can you please add a comment regarding why the delay is required? Does BIOS reset CPL turn on some r […]
I see a similar delay is kept in all the SoCs. So I assume this is for legacy reasons.
Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41777 )
Change subject: soc/intel/jasperlake: add processor power limits control support ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/41777/1/src/soc/intel/jasperlake/sy... File src/soc/intel/jasperlake/systemagent.c:
https://review.coreboot.org/c/coreboot/+/41777/1/src/soc/intel/jasperlake/sy... PS1, Line 69: mdelay(1);
I see a similar delay is kept in all the SoCs. So I assume this is for legacy reasons.
yes that's one of the reason.
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/41777 )
Change subject: soc/intel/jasperlake: add processor power limits control support ......................................................................
soc/intel/jasperlake: add processor power limits control support
Add processor power limits control support to configure values for jasperlake soc based platforms.
BRANCH=None BUG=None TEST=Built for dedede system
Change-Id: Ib5502b225c1158c1f0729ce799ed0b8101f0233f Signed-off-by: Sumeet R Pawnikar sumeet.r.pawnikar@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/41777 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/soc/intel/jasperlake/systemagent.c 1 file changed, 11 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/soc/intel/jasperlake/systemagent.c b/src/soc/intel/jasperlake/systemagent.c index 072db79..080446c 100644 --- a/src/soc/intel/jasperlake/systemagent.c +++ b/src/soc/intel/jasperlake/systemagent.c @@ -1,10 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <device/device.h> +#include <delay.h> #include <device/pci.h> #include <device/pci_ops.h> #include <intelblocks/systemagent.h> +#include <intelblocks/power_limit.h> #include <soc/iomap.h> +#include <soc/soc_chip.h> #include <soc/systemagent.h>
/* @@ -43,9 +46,17 @@ */ void soc_systemagent_init(struct device *dev) { + struct soc_power_limits_config *soc_config; + config_t *config; + /* Enable Power Aware Interrupt Routing */ enable_power_aware_intr();
/* Enable BIOS Reset CPL */ enable_bios_reset_cpl(); + + mdelay(1); + config = config_of_soc(); + soc_config = &config->power_limits_config; + set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config); }
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Karthik Ramasubramanian (Code Review) -
Patrick Georgi (Code Review)
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Sumeet R Pawnikar (Code Review)
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Tim Wawrzynczak (Code Review)