Change in coreboot[master]: mb/google/dedede/var/storo: Add USB2 PHY parameters for LTE USB2.0

[Tao Xia (Code Review)]

Tao Xia has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55511 )

Change subject: mb/google/dedede/var/storo: Add USB2 PHY parameters for LTE USB2.0
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mb/google/dedede/var/storo: Add USB2 PHY parameters for LTE USB2.0

This change adds fine-tuned USB2 PHY parameters for storo.

BUG=191089827
TEST=Built and verified USB2 eye diagram test result

Signed-off-by: Tao Xia 
Change-Id: I38dd8ad59b32f635e641765e0a1bd13651180d23
---
M src/mainboard/google/dedede/variants/storo/overridetree.cb
1 file changed, 9 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/55511/1

diff --git a/src/mainboard/google/dedede/variants/storo/overridetree.cb b/src/mainboard/google/dedede/variants/storo/overridetree.cb
index 6336192..7a5b885 100644
--- a/src/mainboard/google/dedede/variants/storo/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/storo/overridetree.cb
@@ -54,6 +54,15 @@
    	},
    }"

+	register "usb2_ports[3]" = "{
+		.enable = 1,
+		.ocpin = OC_SKIP,
+		.tx_bias = USB2_BIAS_0MV,
+		.tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON,
+		.pre_emp_bias  = USB2_BIAS_28P15MV,
+		.pre_emp_bit   = USB2_HALF_BIT_PRE_EMP,
+	}" # WWAN
+
    register "SerialIoI2cMode" = "{
    	[PchSerialIoIndexI2C0] = PchSerialIoPci,
    	[PchSerialIoIndexI2C1] = PchSerialIoDisabled,