Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43691 )
Change subject: nb/intel/haswell/hostbridge_regs.h: Clean up registers ......................................................................
nb/intel/haswell/hostbridge_regs.h: Clean up registers
Add missing registers and sort them by ascending offsets.
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 does not change.
Change-Id: I98f836668144032d920b56afff878acc0a58ed82 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/haswell/hostbridge_regs.h 1 file changed, 16 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/43691/1
diff --git a/src/northbridge/intel/haswell/hostbridge_regs.h b/src/northbridge/intel/haswell/hostbridge_regs.h index b462a09..75d8b7c 100644 --- a/src/northbridge/intel/haswell/hostbridge_regs.h +++ b/src/northbridge/intel/haswell/hostbridge_regs.h @@ -5,8 +5,6 @@
#define EPBAR 0x40 #define MCHBAR 0x48 -#define PCIEXBAR 0x60 -#define DMIBAR 0x68
#define GGC 0x50 /* GMCH Graphics Control */ #define GGC_DISABLE_VGA_IO_DECODE (1 << 1) @@ -25,6 +23,15 @@ #define DEVEN_D1F2EN (1 << 1) #define DEVEN_D0EN (1 << 0)
+#define PAVPC 0x58 +#define DPR 0x5c + +#define PCIEXBAR 0x60 +#define DMIBAR 0x68 + +#define MESEG_BASE 0x70 /* Management Engine Base */ +#define MESEG_LIMIT 0x78 /* Management Engine Limit */ + #define PAM0 0x80 #define PAM1 0x81 #define PAM2 0x82 @@ -41,8 +48,6 @@ #define G_SMRAME (1 << 3) #define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
-#define MESEG_BASE 0x70 /* Management Engine Base */ -#define MESEG_LIMIT 0x78 /* Management Engine Limit */ #define REMAPBASE 0x90 /* Remap base */ #define REMAPLIMIT 0x98 /* Remap limit */ #define TOM 0xa0 /* Top of DRAM in memory controller space */ @@ -52,9 +57,16 @@ #define TSEG 0xb8 /* TSEG base */ #define TOLUD 0xbc /* Top of Low Used Memory */
+#define ERRSTS 0xc8 +#define ERRCMD 0xca +#define SMICMD 0xcc +#define SCICMD 0xce + #define SKPAD 0xdc /* Scratchpad Data */
#define CAPID0_A 0xe4 #define VTD_DISABLE (1 << 23)
+#define CAPID0_B 0xe8 + #endif /* __HASWELL_HOSTBRIDGE_REGS_H__ */
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43691
to look at the new patch set (#2).
Change subject: nb/intel/haswell/hostbridge_regs.h: Clean up registers ......................................................................
nb/intel/haswell/hostbridge_regs.h: Clean up registers
Add missing registers and sort them by ascending offsets.
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 does not change.
Change-Id: I98f836668144032d920b56afff878acc0a58ed82 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/haswell/hostbridge_regs.h 1 file changed, 18 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/43691/2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43691 )
Change subject: nb/intel/haswell/hostbridge_regs.h: Clean up registers ......................................................................
Patch Set 3:
This change is ready for review.
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43691 )
Change subject: nb/intel/haswell/hostbridge_regs.h: Clean up registers ......................................................................
Patch Set 3: Code-Review+2
Angel Pons has removed a vote from this change. ( https://review.coreboot.org/c/coreboot/+/43691 )
Change subject: nb/intel/haswell/hostbridge_regs.h: Clean up registers ......................................................................
Removed Verified+1 by build bot (Jenkins) no-reply@coreboot.org
Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43691 )
Change subject: nb/intel/haswell/hostbridge_regs.h: Clean up registers ......................................................................
nb/intel/haswell/hostbridge_regs.h: Clean up registers
Add missing registers and sort them by ascending offsets.
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 does not change.
Change-Id: I98f836668144032d920b56afff878acc0a58ed82 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/43691 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Patrick Rudolph siro@das-labor.org --- M src/northbridge/intel/haswell/hostbridge_regs.h 1 file changed, 13 insertions(+), 6 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved
diff --git a/src/northbridge/intel/haswell/hostbridge_regs.h b/src/northbridge/intel/haswell/hostbridge_regs.h index b462a09..f5fa54a 100644 --- a/src/northbridge/intel/haswell/hostbridge_regs.h +++ b/src/northbridge/intel/haswell/hostbridge_regs.h @@ -5,17 +5,15 @@
#define EPBAR 0x40 #define MCHBAR 0x48 -#define PCIEXBAR 0x60 -#define DMIBAR 0x68
-#define GGC 0x50 /* GMCH Graphics Control */ +#define GGC 0x50 /* GMCH Graphics Control */ #define GGC_DISABLE_VGA_IO_DECODE (1 << 1) #define GGC_IGD_MEM_IN_32MB_UNITS(x) (((x) & 0x1f) << 3) #define GGC_GTT_0MB (0 << 8) #define GGC_GTT_1MB (1 << 8) #define GGC_GTT_2MB (2 << 8)
-#define DEVEN 0x54 /* Device Enable */ +#define DEVEN 0x54 /* Device Enable */ #define DEVEN_D7EN (1 << 14) #define DEVEN_D4EN (1 << 7) #define DEVEN_D3EN (1 << 5) @@ -25,6 +23,15 @@ #define DEVEN_D1F2EN (1 << 1) #define DEVEN_D0EN (1 << 0)
+#define PAVPC 0x58 +#define DPR 0x5c + +#define PCIEXBAR 0x60 +#define DMIBAR 0x68 + +#define MESEG_BASE 0x70 /* Management Engine Base */ +#define MESEG_LIMIT 0x78 /* Management Engine Limit */ + #define PAM0 0x80 #define PAM1 0x81 #define PAM2 0x82 @@ -41,8 +48,6 @@ #define G_SMRAME (1 << 3) #define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
-#define MESEG_BASE 0x70 /* Management Engine Base */ -#define MESEG_LIMIT 0x78 /* Management Engine Limit */ #define REMAPBASE 0x90 /* Remap base */ #define REMAPLIMIT 0x98 /* Remap limit */ #define TOM 0xa0 /* Top of DRAM in memory controller space */ @@ -57,4 +62,6 @@ #define CAPID0_A 0xe4 #define VTD_DISABLE (1 << 23)
+#define CAPID0_B 0xe8 + #endif /* __HASWELL_HOSTBRIDGE_REGS_H__ */
-
Angel Pons (Code Review) -
Patrick Rudolph (Code Review)