[XL] Change in coreboot[main]: soc/intel/xeon-sp: Hook up public FSP bin and headers

[Shuo Liu (Code Review)]

Attention is currently required from: Angel Pons, Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Fabian Meyer, Felix Singer, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Srinidhi N Kaushik, Tim Chu.

Shuo Liu has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/80360?usp=email )

Change subject: soc/intel/xeon-sp: Hook up public FSP bin and headers
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Patch Set 4:

(1 comment)

Patchset:

PS3:
> Thanks for working on this. […]

Thanks all for the patience. We confirmed the path to move forward on this together with you.

Public FSP is built with PcdMigrateTemporaryRamFirmwareVolumes = TRUE, where FSP-S will enable paging and breaks the Linux payloads's 32bit kernel handover. Below improvements could help to mitigate.

https://review.coreboot.org/c/coreboot/+/82705
https://review.coreboot.org/c/coreboot/+/82704

Now, CL80360 could boot UEFI and Linux payload (with CL82704/82705) both.