Change in coreboot[master]: src/soc/tigerlake: Add header specific changes for JSP

[Meera Ravindranath (Code Review)]

Hello Ronak Kanabar,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/38754

to review the following change.

Change subject: src/soc/tigerlake: Add header specific changes for JSP
......................................................................

src/soc/tigerlake: Add header specific changes for JSP

Updates the include files in tigerlake soc with JSP specific
changes.

BUG=None
BRANCH=None
TEST=Compilation for jasper lake board is working

Change-Id: Ia8e88e02989fe80d7bd1f28942e005cb0d862fcb
Signed-off-by: Meera Ravindranath 
Signed-off-by: Ronak Kanabar 
---
M src/soc/intel/tigerlake/include/soc/iomap.h
M src/soc/intel/tigerlake/include/soc/irq.h
A src/soc/intel/tigerlake/include/soc/irq_jsl.h
A src/soc/intel/tigerlake/include/soc/irq_tgl.h
4 files changed, 213 insertions(+), 71 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/38754/1

diff --git a/src/soc/intel/tigerlake/include/soc/iomap.h b/src/soc/intel/tigerlake/include/soc/iomap.h
index 2e61477..01f11a5 100644
--- a/src/soc/intel/tigerlake/include/soc/iomap.h
+++ b/src/soc/intel/tigerlake/include/soc/iomap.h
@@ -42,12 +42,6 @@
    				UART_BASE_SIZE * (x)))
 #define UART_BASE(x)		UART_BASE_0_ADDR(x)

-#define EARLY_I2C_BASE_ADDRESS	0xfe020000
-#define EARLY_I2C_BASE(x)	(EARLY_I2C_BASE_ADDRESS + (0x2000 * (x)))
-
-#define MCH_BASE_ADDRESS	0xfedc0000
-#define MCH_BASE_SIZE		0x20000
-
 #define DMI_BASE_ADDRESS	0xfeda0000
 #define DMI_BASE_SIZE		0x1000

@@ -66,7 +60,6 @@
 #define PCH_PWRM_BASE_SIZE	0x10000

#define SPI_BASE_ADDRESS	0xfe010000
-#define EARLY_GSPI_BASE_ADDRESS 0xfe030000

#define GPIO_BASE_SIZE		0x10000

@@ -78,6 +71,28 @@
 #define ABOVE_4GB_MEM_BASE_ADDRESS	(256ULL * GiB)
 #define ABOVE_4GB_MEM_BASE_SIZE	(256ULL * GiB)

+#if CONFIG(SOC_INTEL_TIGERLAKE)
+
+#define MCH_BASE_ADDRESS	0xfedc0000
+#define MCH_BASE_SIZE		0x20000
+
+#define EARLY_GSPI_BASE_ADDRESS 0xfe030000
+
+#define EARLY_I2C_BASE_ADDRESS	0xfe020000
+#define EARLY_I2C_BASE(x)	(EARLY_I2C_BASE_ADDRESS + (0x2000 * (x)))
+
+#else /* CONFIG_SOC_INTEL_JASPERLAKE */
+
+#define MCH_BASE_ADDRESS        0xfea80000
+#define MCH_BASE_SIZE           0x8000
+
+#define EARLY_GSPI_BASE_ADDRESS 0xfe011000
+
+#define EARLY_I2C_BASE_ADDRESS  0xfe040000
+#define EARLY_I2C_BASE(x)       (EARLY_I2C_BASE_ADDRESS + (0x1000 * (x)))
+
+#endif
+
 /*
  * I/O port address space
  */
diff --git a/src/soc/intel/tigerlake/include/soc/irq.h b/src/soc/intel/tigerlake/include/soc/irq.h
index 4d6318f..dec8376 100644
--- a/src/soc/intel/tigerlake/include/soc/irq.h
+++ b/src/soc/intel/tigerlake/include/soc/irq.h
@@ -16,69 +16,10 @@
 #ifndef _SOC_IRQ_H_
 #define _SOC_IRQ_H_

-#define GPIO_IRQ14	14
-#define GPIO_IRQ15	15
+#if CONFIG(SOC_INTEL_TIGERLAKE)
+	#include "irq_tgl.h"
+#else
+	#include "irq_jsl.h"
+#endif /* CONFIG_SOC_INTEL_TIGERLAKE */

-#define PCH_IRQ10	10
-#define PCH_IRQ11	11
-
-#define LPSS_I2C0_IRQ	27
-#define LPSS_I2C1_IRQ	28
-#define LPSS_I2C2_IRQ	29
-#define LPSS_I2C3_IRQ	30
-#define LPSS_I2C4_IRQ	31
-#define LPSS_I2C5_IRQ	32
-#define LPSS_SPI0_IRQ	36
-#define LPSS_SPI1_IRQ	37
-#define LPSS_SPI2_IRQ	18
-#define LPSS_SPI3_IRQ	23
-#define LPSS_UART0_IRQ	34
-#define LPSS_UART1_IRQ	35
-#define LPSS_UART2_IRQ	33
-
-#define HDA_IRQ		16
-#define SMBUS_IRQ	16
-#define TRACEHUB_IRQ	16
-
-#define PCIE_1_IRQ	16
-#define PCIE_2_IRQ	17
-#define PCIE_3_IRQ	18
-#define PCIE_4_IRQ	19
-#define PCIE_5_IRQ	16
-#define PCIE_6_IRQ	17
-#define PCIE_7_IRQ	18
-#define PCIE_8_IRQ	19
-#define PCIE_9_IRQ	16
-#define PCIE_10_IRQ	17
-#define PCIE_11_IRQ	18
-#define PCIE_12_IRQ	19
-
-#define SATA_IRQ	16
-
-#define xHCI_IRQ	16
-#define xDCI_IRQ	17
-#define CNVI_WIFI_IRQ	16
-
-#define CNVI_BT_IRQ	18
-
-#define THC0_IRQ	16
-#define THC1_IRQ	17
-
-#define ISH_IRQ		16
-
-#define TBT_PCIe0_IRQ	16
-#define TBT_PCIe1_IRQ	17
-#define TBT_PCIe2_IRQ	18
-#define TBT_PCIe3_IRQ	19
-
-#define HECI_1_IRQ	16
-#define HECI_2_IRQ	17
-#define HECI_3_IRQ	16
-#define HECI_4_IRQ	19
-
-#define PEG_IRQ		16
-#define IGFX_IRQ	16
-#define THERMAL_IRQ	16
-#define IPU_IRQ		16
-#define GNA_IRQ		16
 #endif /* _SOC_IRQ_H_ */
diff --git a/src/soc/intel/tigerlake/include/soc/irq_jsl.h b/src/soc/intel/tigerlake/include/soc/irq_jsl.h
new file mode 100644
index 0000000..fa94620
--- /dev/null
+++ b/src/soc/intel/tigerlake/include/soc/irq_jsl.h
@@ -0,0 +1,102 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2020 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_JSL_IRQ_H_
+#define _SOC_JSL_IRQ_H_
+
+#define GPIO_IRQ14 14
+#define GPIO_IRQ15 15
+
+#define PCH_IRQ10 10
+#define PCH_IRQ11 11
+
+#define SCI_IRQ9 9
+#define SCI_IRQ10 10
+#define SCI_IRQ11 11
+#define SCI_IRQ20 20
+#define SCI_IRQ21 21
+#define SCI_IRQ22 22
+#define SCI_IRQ23 23
+
+#define TCO_IRQ9 9
+#define TCO_IRQ10 10
+#define TCO_IRQ11 11
+#define TCO_IRQ20 20
+#define TCO_IRQ21 21
+#define TCO_IRQ22 22
+#define TCO_IRQ23 23
+
+#define LPSS_I2C0_IRQ 16
+#define LPSS_I2C1_IRQ 17
+#define LPSS_I2C2_IRQ 18
+#define LPSS_I2C3_IRQ 19
+#define LPSS_I2C4_IRQ 32
+#define LPSS_I2C5_IRQ 33
+#define LPSS_SPI0_IRQ 22
+#define LPSS_SPI1_IRQ 23
+#define LPSS_SPI2_IRQ 24
+#define LPSS_UART0_IRQ 20
+#define LPSS_UART1_IRQ 21
+#define LPSS_UART2_IRQ 34
+#define SDIO_IRQ 22
+
+#define cAVS_INTA_IRQ 16
+#define SMBUS_INTA_IRQ 16
+#define SMBUS_INTB_IRQ 17
+#define GbE_INTA_IRQ 16
+#define GbE_INTC_IRQ 18
+#define TRACE_HUB_INTA_IRQ 16
+#define TRACE_HUB_INTD_IRQ 19
+
+#define eMMC_IRQ 16
+#define SD_IRQ 19
+
+#define PCIE_1_IRQ 16
+#define PCIE_2_IRQ 17
+#define PCIE_3_IRQ 18
+#define PCIE_4_IRQ 19
+#define PCIE_5_IRQ 16
+#define PCIE_6_IRQ 17
+#define PCIE_7_IRQ 18
+#define PCIE_8_IRQ 19
+
+#define SATA_IRQ 16
+
+#define HECI_1_IRQ 16
+#define HECI_2_IRQ 17
+#define IDER_IRQ 18
+#define KT_IRQ 19
+#define HECI_3_IRQ 16
+
+#define XHCI_IRQ 16
+#define OTG_IRQ 17
+#define PMC_SRAM_IRQ 18
+#define THERMAL_IRQ 16
+#define CNViWIFI_IRQ 19
+#define UFS_IRQ 16
+#define CIO_INTA_IRQ 16
+#define CIO_INTD_IRQ 19
+#define ISH_IRQ 20
+
+#define PEG_RP_INTA_IRQ 16
+#define PEG_RP_INTB_IRQ 17
+#define PEG_RP_INTC_IRQ 18
+#define PEG_RP_INTD_IRQ 19
+
+#define IGFX_IRQ 16
+#define SA_THERMAL_IRQ 16
+#define IPU_IRQ 16
+#define GNA_IRQ 16
+#endif /* _JSL_IRQ_H_ */
diff --git a/src/soc/intel/tigerlake/include/soc/irq_tgl.h b/src/soc/intel/tigerlake/include/soc/irq_tgl.h
new file mode 100644
index 0000000..2a446a6
--- /dev/null
+++ b/src/soc/intel/tigerlake/include/soc/irq_tgl.h
@@ -0,0 +1,84 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2020 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_TGL_IRQ_H_
+#define _SOC_TGL_IRQ_H_
+
+#define GPIO_IRQ14	14
+#define GPIO_IRQ15	15
+
+#define PCH_IRQ10	10
+#define PCH_IRQ11	11
+
+#define LPSS_I2C0_IRQ	27
+#define LPSS_I2C1_IRQ	28
+#define LPSS_I2C2_IRQ	29
+#define LPSS_I2C3_IRQ	30
+#define LPSS_I2C4_IRQ	31
+#define LPSS_I2C5_IRQ	32
+#define LPSS_SPI0_IRQ	36
+#define LPSS_SPI1_IRQ	37
+#define LPSS_SPI2_IRQ	18
+#define LPSS_SPI3_IRQ	23
+#define LPSS_UART0_IRQ	34
+#define LPSS_UART1_IRQ	35
+#define LPSS_UART2_IRQ	33
+
+#define HDA_IRQ		16
+#define SMBUS_IRQ	16
+#define TRACEHUB_IRQ	16
+
+#define PCIE_1_IRQ	16
+#define PCIE_2_IRQ	17
+#define PCIE_3_IRQ	18
+#define PCIE_4_IRQ	19
+#define PCIE_5_IRQ	16
+#define PCIE_6_IRQ	17
+#define PCIE_7_IRQ	18
+#define PCIE_8_IRQ	19
+#define PCIE_9_IRQ	16
+#define PCIE_10_IRQ	17
+#define PCIE_11_IRQ	18
+#define PCIE_12_IRQ	19
+
+#define SATA_IRQ	16
+
+#define xHCI_IRQ	16
+#define xDCI_IRQ	17
+#define CNVI_WIFI_IRQ	16
+
+#define CNVI_BT_IRQ	18
+
+#define THC0_IRQ	16
+#define THC1_IRQ	17
+
+#define ISH_IRQ		16
+
+#define TBT_PCIe0_IRQ	16
+#define TBT_PCIe1_IRQ	17
+#define TBT_PCIe2_IRQ	18
+#define TBT_PCIe3_IRQ	19
+
+#define HECI_1_IRQ	16
+#define HECI_2_IRQ	17
+#define HECI_3_IRQ	16
+#define HECI_4_IRQ	19
+
+#define PEG_IRQ		16
+#define IGFX_IRQ	16
+#define THERMAL_IRQ	16
+#define IPU_IRQ		16
+#define GNA_IRQ		16
+#endif /* _SOC_IRQ_H_ */

[Meera Ravindranath (Code Review)]

Hello Patrick Rudolph, Karthik Ramasubramanian, Aamir Bohra, Ronak Kanabar, Rizwan Qureshi, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38754

to look at the new patch set (#2).

Change subject: src/soc/tigerlake: Add header specific changes for JSP
......................................................................

src/soc/tigerlake: Add header specific changes for JSP

Updates the include files in tigerlake soc with JSP specific
changes.

BUG=None
BRANCH=None
TEST=Compilation for jasper lake board is working

Change-Id: Ia8e88e02989fe80d7bd1f28942e005cb0d862fcb
Signed-off-by: Meera Ravindranath 
Signed-off-by: Ronak Kanabar 
---
M src/soc/intel/tigerlake/include/soc/iomap.h
1 file changed, 22 insertions(+), 7 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/38754/2

Change in coreboot[master]: src/soc/tigerlake: Add IOmap header changes for JSP

[Meera Ravindranath (Code Review)]

Hello Patrick Rudolph, Karthik Ramasubramanian, Aamir Bohra, Ronak Kanabar, Rizwan Qureshi, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38754

to look at the new patch set (#3).

Change subject: src/soc/tigerlake: Add IOmap header changes for JSP
......................................................................

src/soc/tigerlake: Add IOmap header changes for JSP

Updating MCH, GSPI And I2C base addresses for JSP in iomap header.

BUG=None
BRANCH=None
TEST=Compilation for jasper lake board is working

Change-Id: Ia8e88e02989fe80d7bd1f28942e005cb0d862fcb
Signed-off-by: Meera Ravindranath 
Signed-off-by: Ronak Kanabar 
---
M src/soc/intel/tigerlake/include/soc/iomap.h
1 file changed, 22 insertions(+), 7 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/38754/3

Change in coreboot[master]: src/soc/tigerlake: Add IOmap header changes for JSP

[Karthik Ramasubramanian (Code Review)]

Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38754 )

Change subject: src/soc/tigerlake: Add IOmap header changes for JSP
......................................................................

Patch Set 3: Code-Review+2

Change in coreboot[master]: src/soc/tigerlake: Add IOmap header changes for JSP

[Aamir Bohra (Code Review)]

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38754 )

Change subject: src/soc/tigerlake: Add IOmap header changes for JSP
......................................................................

Patch Set 3: Code-Review+2

Change in coreboot[master]: src/soc/tigerlake: Add IOmap header changes for JSP

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38754 )

Change subject: src/soc/tigerlake: Add IOmap header changes for JSP
......................................................................

Patch Set 3:

(6 comments)

https://review.coreboot.org/c/coreboot/+/38754/3//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/38754/3//COMMIT_MSG@7 
PS3, Line 7: IOmap 
iomap
else you can write as 
"Accommodate JSP specific changes in iomap.h"

https://review.coreboot.org/c/coreboot/+/38754/3/src/soc/intel/tigerlake/inc... 
File src/soc/intel/tigerlake/include/soc/iomap.h:

https://review.coreboot.org/c/coreboot/+/38754/3/src/soc/intel/tigerlake/inc... 
PS3, Line 86:         
Prefer tab over white space

https://review.coreboot.org/c/coreboot/+/38754/3/src/soc/intel/tigerlake/inc... 
PS3, Line 87: #define MCH_BASE_SIZE           0x8000
same

https://review.coreboot.org/c/coreboot/+/38754/3/src/soc/intel/tigerlake/inc... 
PS3, Line 89: #define EARLY_GSPI_BASE_ADDRESS 0xfe011000
same

https://review.coreboot.org/c/coreboot/+/38754/3/src/soc/intel/tigerlake/inc... 
PS3, Line 91: #define EARLY_I2C_BASE_ADDRESS  0xfe040000
same

https://review.coreboot.org/c/coreboot/+/38754/3/src/soc/intel/tigerlake/inc... 
PS3, Line 92: #define EARLY_I2C_BASE(x)       (EARLY_I2C_BASE_ADDRESS + (0x1000 * (x)))
same

Change in coreboot[master]: src/soc/tigerlake: Accomodate JSP specific changes in iomap.h

[Meera Ravindranath (Code Review)]

Hello Patrick Rudolph, Karthik Ramasubramanian, Aamir Bohra, Ronak Kanabar, Rizwan Qureshi, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38754

to look at the new patch set (#4).

Change subject: src/soc/tigerlake: Accomodate JSP specific changes in iomap.h
......................................................................

src/soc/tigerlake: Accomodate JSP specific changes in iomap.h

Updating MCH, GSPI And I2C base addresses for JSP in iomap header.

BUG=None
BRANCH=None
TEST=Compilation for Jasper lake board is working

Change-Id: Ia8e88e02989fe80d7bd1f28942e005cb0d862fcb
Signed-off-by: Meera Ravindranath 
Signed-off-by: Ronak Kanabar 
---
M src/soc/intel/tigerlake/include/soc/iomap.h
1 file changed, 22 insertions(+), 7 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/38754/4

Change in coreboot[master]: src/soc/tigerlake: Accomodate JSP specific changes in iomap.h

[Meera Ravindranath (Code Review)]

Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38754 )

Change subject: src/soc/tigerlake: Accomodate JSP specific changes in iomap.h
......................................................................

Patch Set 4:

(6 comments)

https://review.coreboot.org/c/coreboot/+/38754/3//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/38754/3//COMMIT_MSG@7 
PS3, Line 7: IOmap
> iomap […]

Done

https://review.coreboot.org/c/coreboot/+/38754/3/src/soc/intel/tigerlake/inc... 
File src/soc/intel/tigerlake/include/soc/iomap.h:

https://review.coreboot.org/c/coreboot/+/38754/3/src/soc/intel/tigerlake/inc... 
PS3, Line 86:
> Prefer tab over white space

Done

https://review.coreboot.org/c/coreboot/+/38754/3/src/soc/intel/tigerlake/inc... 
PS3, Line 87: #define MCH_BASE_SIZE           0x8000
> same

Done

https://review.coreboot.org/c/coreboot/+/38754/3/src/soc/intel/tigerlake/inc... 
PS3, Line 89: #define EARLY_GSPI_BASE_ADDRESS 0xfe011000
> same

Done

https://review.coreboot.org/c/coreboot/+/38754/3/src/soc/intel/tigerlake/inc... 
PS3, Line 91: #define EARLY_I2C_BASE_ADDRESS  0xfe040000
> same

Done

https://review.coreboot.org/c/coreboot/+/38754/3/src/soc/intel/tigerlake/inc... 
PS3, Line 92: #define EARLY_I2C_BASE(x)       (EARLY_I2C_BASE_ADDRESS + (0x1000 * (x)))
> same

Done

Change in coreboot[master]: src/soc/tigerlake: Accomodate JSP specific changes in iomap.h

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38754 )

Change subject: src/soc/tigerlake: Accomodate JSP specific changes in iomap.h
......................................................................

Patch Set 4: Code-Review+2

Change in coreboot[master]: src/soc/tigerlake: Accomodate JSP specific changes in iomap.h

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38754 )

Change subject: src/soc/tigerlake: Accomodate JSP specific changes in iomap.h
......................................................................

src/soc/tigerlake: Accomodate JSP specific changes in iomap.h

Updating MCH, GSPI And I2C base addresses for JSP in iomap header.

BUG=None
BRANCH=None
TEST=Compilation for Jasper lake board is working

Change-Id: Ia8e88e02989fe80d7bd1f28942e005cb0d862fcb
Signed-off-by: Meera Ravindranath 
Signed-off-by: Ronak Kanabar 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38754
Reviewed-by: Subrata Banik 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/tigerlake/include/soc/iomap.h
1 file changed, 22 insertions(+), 7 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Subrata Banik: Looks good to me, approved

diff --git a/src/soc/intel/tigerlake/include/soc/iomap.h b/src/soc/intel/tigerlake/include/soc/iomap.h
index 2e61477..f403873 100644
--- a/src/soc/intel/tigerlake/include/soc/iomap.h
+++ b/src/soc/intel/tigerlake/include/soc/iomap.h
@@ -42,12 +42,6 @@
    				UART_BASE_SIZE * (x)))
 #define UART_BASE(x)		UART_BASE_0_ADDR(x)

-#define EARLY_I2C_BASE_ADDRESS	0xfe020000
-#define EARLY_I2C_BASE(x)	(EARLY_I2C_BASE_ADDRESS + (0x2000 * (x)))
-
-#define MCH_BASE_ADDRESS	0xfedc0000
-#define MCH_BASE_SIZE		0x20000
-
 #define DMI_BASE_ADDRESS	0xfeda0000
 #define DMI_BASE_SIZE		0x1000

@@ -66,7 +60,6 @@
 #define PCH_PWRM_BASE_SIZE	0x10000

#define SPI_BASE_ADDRESS	0xfe010000
-#define EARLY_GSPI_BASE_ADDRESS 0xfe030000

#define GPIO_BASE_SIZE		0x10000

@@ -78,6 +71,28 @@
 #define ABOVE_4GB_MEM_BASE_ADDRESS	(256ULL * GiB)
 #define ABOVE_4GB_MEM_BASE_SIZE	(256ULL * GiB)

+#if CONFIG(SOC_INTEL_TIGERLAKE)
+
+#define MCH_BASE_ADDRESS	0xfedc0000
+#define MCH_BASE_SIZE		0x20000
+
+#define EARLY_GSPI_BASE_ADDRESS 0xfe030000
+
+#define EARLY_I2C_BASE_ADDRESS	0xfe020000
+#define EARLY_I2C_BASE(x)	(EARLY_I2C_BASE_ADDRESS + (0x2000 * (x)))
+
+#else /* CONFIG_SOC_INTEL_JASPERLAKE */
+
+#define MCH_BASE_ADDRESS	0xfea80000
+#define MCH_BASE_SIZE		0x8000
+
+#define EARLY_GSPI_BASE_ADDRESS	0xfe011000
+
+#define EARLY_I2C_BASE_ADDRESS	0xfe040000
+#define EARLY_I2C_BASE(x)	(EARLY_I2C_BASE_ADDRESS + (0x1000 * (x)))
+
+#endif
+
 /*
  * I/O port address space
  */