Change in coreboot[master]: soc/amd/common/block/lpc/spi_dma: Implement SPI DMA functionality

[Eric Peers (Code Review)]

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held.
Eric Peers has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56228 )

Change subject: soc/amd/common/block/lpc/spi_dma: Implement SPI DMA functionality
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Patch Set 2:

(3 comments)

File src/soc/amd/common/block/lpc/spi_dma.c:

https://review.coreboot.org/c/coreboot/+/56228/comment/b62dc5b3_3b74e308 
PS2, Line 69: 	if (!IS_ALIGNED((uintptr_t)target, LPC_ROM_DMA_MIN_ALIGNMENT))
given your comments about architectural constraints (RN, CZN+), do we need a check for that as well?

https://review.coreboot.org/c/coreboot/+/56228/comment/95931424_b6c56a3d 
PS2, Line 119: 	if (spi_dma_has_error())
does this need to move above the busy check?

https://review.coreboot.org/c/coreboot/+/56228/comment/b5a7ca4a_9cb8726c 
PS2, Line 158: 		udelay(10);
why 10? will different spi speeds yield a different number here?