[XS] Change in coreboot[main]: mb/google/fatcat/var/felino: Use GPP_E03 for EC_SYNC_IRQ

[Tongtong Pan (Code Review)]

Tongtong Pan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87210?usp=email )

Change subject: mb/google/fatcat/var/felino: Use GPP_E03 for EC_SYNC_IRQ
......................................................................

mb/google/fatcat/var/felino: Use GPP_E03 for EC_SYNC_IRQ

Use GPP_E03 as the EC sync interrupt and provide this value
to the embedded controller to be exported to the OS.

BUG=b:403383143
Test=emerge-fatcat coreboot and Confirm the log:
cros_ec_lpcs GOOG0004:00: Chrome EC device registered

Change-Id: If7d120fcf2de8dbbbc399d2ead4e294d11ea8a14
Signed-off-by: Tongtong Pan 
---
M src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h
M src/mainboard/google/fatcat/variants/felino/gpio.c
2 files changed, 3 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/87210/1

diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h b/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h
index dc4ce13..a5772a4 100644
--- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h
+++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h
@@ -26,8 +26,8 @@
 /* Used to gate SoC's SLP_S0# signal */
 #define GPIO_SLP_S0_GATE	GPP_F23
 #elif CONFIG(BOARD_GOOGLE_FELINO)
- #define EC_SYNC_IRQ	0 /* TODO */
- #define GPIO_PCH_WP	0 /* TODO */
+ #define EC_SYNC_IRQ	GPP_E03_IRQ
+ #define GPIO_PCH_WP	0
 /* Used to gate SoC's SLP_S0# signal */
 #define GPIO_SLP_S0_GATE	GPP_D03
 #endif
diff --git a/src/mainboard/google/fatcat/variants/felino/gpio.c b/src/mainboard/google/fatcat/variants/felino/gpio.c
index 3b2a693..f5f9852 100644
--- a/src/mainboard/google/fatcat/variants/felino/gpio.c
+++ b/src/mainboard/google/fatcat/variants/felino/gpio.c
@@ -207,7 +207,7 @@
    /* GPP_E02:     NC  */
    PAD_NC(GPP_E02, NONE),
    /* GPP_E03:     NC */
-	PAD_NC(GPP_E03, NONE),
+	PAD_CFG_GPI_APIC(GPP_E03, NONE, PLTRST, LEVEL, INVERT),
    /* GPP_E05:     NC */
    PAD_NC(GPP_E05, NONE),
    /* GPP_E06:     GPP_E06 */