Change in coreboot[master]: soc/amd/cezanne: Enable ACPI_SOC_NVS

[Raul Rangel (Code Review)]

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50614 )

Change subject: soc/amd/cezanne: Enable ACPI_SOC_NVS
......................................................................

soc/amd/cezanne: Enable ACPI_SOC_NVS

This fixes the undefined reference for NVB0, NVB1, and NVB2.

Signed-off-by: Raul E Rangel 
Change-Id: Ib4ba24b66b9ae7899ccd40f91cdd23074f6afc4b
---
M src/soc/amd/cezanne/Kconfig
1 file changed, 1 insertion(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/50614/1

diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index 50754a9..9e09d8a 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -9,6 +9,7 @@

config SOC_SPECIFIC_OPTIONS
    def_bool y
+	select ACPI_SOC_NVS
    select ARCH_BOOTBLOCK_X86_32
    select ARCH_VERSTAGE_X86_32
    select ARCH_ROMSTAGE_X86_32