Change in coreboot[master]: arch/x86: Refactor the SMBIOS type 17 write function

[Subrata Banik (Code Review)]

Attention is currently required from: Jason Glenesk, Jakub Czapiga, Marshall Dawson, Tim Wawrzynczak, Angel Pons, Rob Barnes, Patrick Rudolph, Felix Held.
Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Furquan Shaikh, Jakub Czapiga, Marshall Dawson, Tim Wawrzynczak, Angel Pons, Rob Barnes, Patrick Rudolph, Felix Held,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/56628

to look at the new patch set (#18).

Change subject: arch/x86: Refactor the SMBIOS type 17 write function
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arch/x86: Refactor the SMBIOS type 17 write function

List of changes:
1. Create Module Type macros as per Memory Type
(i.e. DDR2/DDR3/DDR4/DDR5/LPDDR4/LPDDR5) and fix compilation
issue due to renaming of existing macros due to scoping the Memory
Type.
2. Use dedicated Memory Type and Module type for `Form Factor`
and `TypeDetail` conversion using `get_spd_info()` function.
3. Create a new API (convert_form_factor_to_module_type()) for
`Form Factor` to 'Module type' conversion as per `Memory Type`.
4. Add new argument as `Memory Type` to
smbios_form_factor_to_spd_mod_type() so that
smbios_form_factor_to_spd_mod_type() can internally call
convert_form_factor_to_module_type() for `Module Type` conversion.
5. Update `test_smbios_form_factor_to_spd_mod_type()` to
accommodate different memory types.

Refer to datasheet SPD4.1.2.M-1 for LPDDRx and SPD4.1.2.L-3 for DDRx.

BUG=b:194659789
TEST=Refer to dmidecode -t 17 output as below:
Without this code change:

Handle 0x0012, DMI type 17, 40 bytes
Memory Device
        Array Handle: 0x000A
        Error Information Handle: Not Provided
        Total Width: 16 bits
        Data Width: 16 bits
        Size: 2048 MB
        Form Factor: Unknown
        ....

With this code change:

Handle 0x0012, DMI type 17, 40 bytes
Memory Device
        Array Handle: 0x000A
        Error Information Handle: Not Provided
        Total Width: 16 bits
        Data Width: 16 bits
        Size: 2048 MB
        Form Factor: Row Of Chips
        ....

Change-Id: Ia337ac8f50b61ae78d86a07c7a86aa9c248bad50
Signed-off-by: Subrata Banik 
---
M src/arch/x86/smbios.c
M src/device/dram/ddr3.c
M src/device/dram/ddr4.c
M src/device/dram/spd.c
M src/include/device/dram/spd.h
M src/include/dimm_info_util.h
M src/include/spd.h
M src/lib/dimm_info_util.c
M src/mainboard/scaleway/tagada/ramstage.c
M src/northbridge/intel/haswell/haswell_mrc/raminit.c
M src/soc/amd/common/fsp/dmi.c
M src/soc/amd/common/pi/amd_late_init.c
M tests/lib/Makefile.inc
M tests/lib/dimm_info_util-test.c
14 files changed, 444 insertions(+), 86 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/56628/18