[S] Change in coreboot[master]: mb/siemens/mc_ehl5: Disable PCIe RP7

[Mario Scheithauer (Code Review)]

Attention is currently required from: Werner Zeh.

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74937 )

Change subject: mb/siemens/mc_ehl5: Disable PCIe RP7
......................................................................

mb/siemens/mc_ehl5: Disable PCIe RP7

This mainboard does not use legacy PCI devices behinde a PCIe-2-PCI
bridge like the mc_ehl2 mainboard does. Therfore PCIe RP7 is disabled
and all functionality for it is removed.

Change-Id: I768fe4b31abbc9a3c47149020439ee534bb5c443
Signed-off-by: Mario Scheithauer 
---
M src/mainboard/siemens/mc_ehl/mainboard.c
M src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb
M src/mainboard/siemens/mc_ehl/variants/mc_ehl5/mainboard.c
3 files changed, 17 insertions(+), 13 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/74937/1

diff --git a/src/mainboard/siemens/mc_ehl/mainboard.c b/src/mainboard/siemens/mc_ehl/mainboard.c
index 7aa0d86..db72123 100644
--- a/src/mainboard/siemens/mc_ehl/mainboard.c
+++ b/src/mainboard/siemens/mc_ehl/mainboard.c
@@ -95,6 +95,9 @@
    uint32_t legacy_delay, us_since_boot;
    struct stopwatch sw;

+	if (CONFIG(BOARD_SIEMENS_MC_EHL5))
+		return;
+
    /* Open main hwinfo block. */
    if (hwilib_find_blocks("hwinfo.hex") != CB_SUCCESS)
    	return;
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb
index 53ea1f6..31002c0 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb
@@ -41,7 +41,6 @@

# PCIe root ports related UPDs
    register "PcieRpEnable[1]" = "1"
-	register "PcieRpEnable[6]" = "1"

register "PcieClkSrcUsage[0]" = "PCIE_CLK_NOTUSED"
    register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE"
@@ -59,11 +58,9 @@

# Disable all L1 substates for PCIe root ports
    register "PcieRpL1Substates[1]" = "L1_SS_DISABLED"
-	register "PcieRpL1Substates[6]" = "L1_SS_DISABLED"

# Disable LTR for all PCIe root ports
    register "PcieRpLtrDisable[1]" = "true"
-	register "PcieRpLtrDisable[6]" = "true"

# Storage (SDCARD/EMMC) related UPDs
    register "ScsEmmcHs400Enabled" = "0"
@@ -184,7 +181,6 @@
    	device pci 1a.1 on	end # SD

device pci 1c.1 on	end # RP2 (pcie0 single VC)
-		device pci 1c.6 on	end # RP7 (pcie3 multi VC)

device pci 1d.0 off	end # Intel PSE IPC (local host to PSE)
    	device pci 1d.1 on	    # Intel PSE Time-Sensitive Networking GbE 0
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/mainboard.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/mainboard.c
index 1121399..0930cae 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/mainboard.c
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/mainboard.c
@@ -21,15 +21,6 @@
 {
    struct device *dev;

-	/* PIR8 register mapping for PCIe root ports
-	   INTA#->PIRQC#, INTB#->PIRQD#, INTC#->PIRQA#, INTD#-> PIRQB# */
-	pcr_write16(PID_ITSS, 0x3150, 0x1032);
-
-	/* Disable clock outputs 1-5 (CLKOUT) for XIO2001 PCIe to PCI Bridge. */
-	dev = dev_find_device(PCI_VID_TI, PCI_DID_TI_XIO2001, 0);
-	if (dev)
-		pci_write_config8(dev, 0xd8, 0x3e);
-
    /* Limit SD-Card speed to DDR50 mode to avoid SDR104/SDR50 modes due to
       layout limitations. */
    dev = pcidev_path_on_root(PCH_DEVFN_SDCARD);