Change in coreboot[master]: vendercode/intel/fsp/fsp2_0/glk: Update FSP header file per v2.2.0
Hello SH Kim,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/44435
to review the following change.
Change subject: vendercode/intel/fsp/fsp2_0/glk: Update FSP header file per v2.2.0 ......................................................................
vendercode/intel/fsp/fsp2_0/glk: Update FSP header file per v2.2.0
Update FSP header file to match GLK FSP v2.2.0
BUG=none BRANCH=none TEST=none
Change-Id: I515b4c44439e3404d3b06d587f0846457000fdb4 Signed-off-by: Seunghwan Kim sh_.kim@samsung.corp-partner.google.com --- M src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h 1 file changed, 15 insertions(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/44435/1
diff --git a/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h index 97a40b6..0d3902d 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h @@ -1715,33 +1715,33 @@ **/ UINT8 SkipSpiPCP;
-/** Offset 0x03AB - PMIC PCH_PWROK delay configuration - IPC Configuration - Upd for changing PCH_PWROK delay configuration : I2C_Slave_Address (31:24) + Register_Offset - (23:16) + OR Value (15:8) + AND Value (7:0) -**/ - UINT32 PmicPmcIpcCtrl; - -/** Offset 0x03AF - ModPhyIfValue +/** Offset 0x03AB - ModPhyIfValue Upd To modify the Integrated Filter (IF) value as 0x12(Default) for WIN and 0x16 for Chrome **/ UINT8 ModPhyIfValue;
-/** Offset 0x03B0 - ModPhyVoltageBump - ModPhyVoltageBump. 1: enable, 0: disable - $EN_DIS +/** Offset 0x03AC - PMIC PCH_PWROK delay configuration - IPC Configuration + Upd for changing PCH_PWROK delay configuration : I2C_Slave_Address (31:24) + Register_Offset + (23:16) + OR Value (15:8) + AND Value (7:0) **/ - UINT8 ModPhyVoltageBump; + UINT32 PmicPmcIpcCtrl;
-/** Offset 0x03B1 - Vdd2 Voltage configuration +/** Offset 0x03B0 - Vdd2 Voltage configuration Upd for changing Vdd2 Voltage configuration : I2C_Slave_Address (31:23) + Register_Offset (23:16) + OR Value (15:8) + AND Value (7:0) **/ UINT32 PmicVdd2Voltage;
+/** Offset 0x03B4 - ModPhyVoltageBump + ModPhyVoltageBump. 1: enable, 0: disable + $EN_DIS +**/ + UINT8 ModPhyVoltageBump; + /** Offset 0x03B5 **/ - UINT8 ReservedFspsUpd[1]; + UINT8 ReservedFspsUpd[3]; } FSP_S_CONFIG;
/** Fsp S SGX Configuration @@ -1810,9 +1810,9 @@ **/ FSP_S_CONFIG FspsConfig;
-/** Offset 0x03B6 +/** Offset 0x03B8 **/ - UINT8 UnusedUpdSpace7[10]; + UINT8 UnusedUpdSpace7[8];
/** Offset 0x03C0 **/
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44435 )
Change subject: vendercode/intel/fsp/fsp2_0/glk: Update FSP header file per v2.2.0 ......................................................................
Patch Set 1:
Adding Karthik. What is the plan to handle this on octopus firmware branch? Does this require FSP uprev?
shkim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44435 )
Change subject: vendercode/intel/fsp/fsp2_0/glk: Update FSP header file per v2.2.0 ......................................................................
Patch Set 1:
firmware-octopus-11297.B branch is using FSP v2.2.0 already. We met USB 3.0 device detection issue on that branch due to mismatching of FSP UPD parameter offset. (b:163382089)
Marx Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44435 )
Change subject: vendercode/intel/fsp/fsp2_0/glk: Update FSP header file per v2.2.0 ......................................................................
Patch Set 1: Code-Review+1
Marx Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44435 )
Change subject: vendercode/intel/fsp/fsp2_0/glk: Update FSP header file per v2.2.0 ......................................................................
Patch Set 1:
Patch Set 1:
Adding Karthik. What is the plan to handle this on octopus firmware branch? Does this require FSP uprev?
1. it does not require FSP uprev. 2. when new FSP is released, we need to sync the Fsp UPD header files between coreboot and FSP if they're updated.like Ex, https://review.coreboot.org/c/coreboot/+/29363/ when FSP 2.0.7.1 was released. 3. when FSP 2.2.0.0 was released, to sync the header file is missed.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44435 )
Change subject: vendercode/intel/fsp/fsp2_0/glk: Update FSP header file per v2.2.0 ......................................................................
Patch Set 1: Code-Review+2
Patch Set 1:
Patch Set 1:
Adding Karthik. What is the plan to handle this on octopus firmware branch? Does this require FSP uprev?
- it does not require FSP uprev.
- when new FSP is released, we need to sync the Fsp UPD header files between coreboot and FSP if they're updated.like Ex, https://review.coreboot.org/c/coreboot/+/29363/ when FSP 2.0.7.1 was released.
- when FSP 2.2.0.0 was released, to sync the header file is missed.
I'm surprised that the UPD hash didn't complain because of a new version? But this matches what's in the FSP headers
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44435 )
Change subject: vendercode/intel/fsp/fsp2_0/glk: Update FSP header file per v2.2.0 ......................................................................
Patch Set 1: Code-Review+2
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44435 )
Change subject: vendercode/intel/fsp/fsp2_0/glk: Update FSP header file per v2.2.0 ......................................................................
Patch Set 1: Code-Review+2
Karthik Ramasubramanian has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44435 )
Change subject: vendercode/intel/fsp/fsp2_0/glk: Update FSP header file per v2.2.0 ......................................................................
vendercode/intel/fsp/fsp2_0/glk: Update FSP header file per v2.2.0
Update FSP header file to match GLK FSP v2.2.0
BUG=none BRANCH=none TEST=none
Change-Id: I515b4c44439e3404d3b06d587f0846457000fdb4 Signed-off-by: Seunghwan Kim sh_.kim@samsung.corp-partner.google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/44435 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Marx Wang marx.wang@intel.com Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org Reviewed-by: Furquan Shaikh furquan@google.com Reviewed-by: Karthik Ramasubramanian kramasub@google.com --- M src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h 1 file changed, 15 insertions(+), 15 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Marx Wang: Looks good to me, but someone else must approve Karthik Ramasubramanian: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h index 97a40b6..0d3902d 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h @@ -1715,33 +1715,33 @@ **/ UINT8 SkipSpiPCP;
-/** Offset 0x03AB - PMIC PCH_PWROK delay configuration - IPC Configuration - Upd for changing PCH_PWROK delay configuration : I2C_Slave_Address (31:24) + Register_Offset - (23:16) + OR Value (15:8) + AND Value (7:0) -**/ - UINT32 PmicPmcIpcCtrl; - -/** Offset 0x03AF - ModPhyIfValue +/** Offset 0x03AB - ModPhyIfValue Upd To modify the Integrated Filter (IF) value as 0x12(Default) for WIN and 0x16 for Chrome **/ UINT8 ModPhyIfValue;
-/** Offset 0x03B0 - ModPhyVoltageBump - ModPhyVoltageBump. 1: enable, 0: disable - $EN_DIS +/** Offset 0x03AC - PMIC PCH_PWROK delay configuration - IPC Configuration + Upd for changing PCH_PWROK delay configuration : I2C_Slave_Address (31:24) + Register_Offset + (23:16) + OR Value (15:8) + AND Value (7:0) **/ - UINT8 ModPhyVoltageBump; + UINT32 PmicPmcIpcCtrl;
-/** Offset 0x03B1 - Vdd2 Voltage configuration +/** Offset 0x03B0 - Vdd2 Voltage configuration Upd for changing Vdd2 Voltage configuration : I2C_Slave_Address (31:23) + Register_Offset (23:16) + OR Value (15:8) + AND Value (7:0) **/ UINT32 PmicVdd2Voltage;
+/** Offset 0x03B4 - ModPhyVoltageBump + ModPhyVoltageBump. 1: enable, 0: disable + $EN_DIS +**/ + UINT8 ModPhyVoltageBump; + /** Offset 0x03B5 **/ - UINT8 ReservedFspsUpd[1]; + UINT8 ReservedFspsUpd[3]; } FSP_S_CONFIG;
/** Fsp S SGX Configuration @@ -1810,9 +1810,9 @@ **/ FSP_S_CONFIG FspsConfig;
-/** Offset 0x03B6 +/** Offset 0x03B8 **/ - UINT8 UnusedUpdSpace7[10]; + UINT8 UnusedUpdSpace7[8];
/** Offset 0x03C0 **/
-
Furquan Shaikh (Code Review) -
Karthik Ramasubramanian (Code Review)
-
Marx Wang (Code Review)
-
shkim (Code Review)
-
Tim Wawrzynczak (Code Review)