Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45291 )
Change subject: mb/intel/tglrvp: Add DTT support for tglrvp ......................................................................
mb/intel/tglrvp: Add DTT support for tglrvp
Add DTT (Dynamic Tuning Technology) support for Tiger Lake based rvp board. Set power limits and CPU sensor thresholds for DTT based thermal control.
BRANCH=None BUG=Noe TEST=Build and boot on tglrvp board
Change-Id: I0dbee370b8dc9e1e3ae6f1a1101047ac6fd76f53 Signed-off-by: Sumeet R Pawnikar sumeet.r.pawnikar@intel.com --- M src/mainboard/intel/tglrvp/Kconfig M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb 3 files changed, 85 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/45291/1
diff --git a/src/mainboard/intel/tglrvp/Kconfig b/src/mainboard/intel/tglrvp/Kconfig index c94cca6..53df820 100644 --- a/src/mainboard/intel/tglrvp/Kconfig +++ b/src/mainboard/intel/tglrvp/Kconfig @@ -3,16 +3,19 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_32768 + select DPTF_USE_EISA_HID select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select MAINBOARD_HAS_CHROMEOS select DRIVERS_I2C_HID + select DRIVERS_INTEL_DPTF select DRIVERS_I2C_GENERIC select DRIVERS_I2C_MAX98373 select DRIVERS_INTEL_PMC select DRIVERS_USB_ACPI select DRIVERS_SPI_ACPI select SOC_INTEL_TIGERLAKE + select SOC_INTEL_COMMON_BLOCK_DTT select INTEL_LPSS_UART_FOR_CONSOLE select DRIVERS_INTEL_ISH select EC_ACPI diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index d4390b0..e254e37 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -115,6 +115,24 @@ # Enable S0ix register "s0ix_enable" = "1"
+ # Enable DPTF + register "dptf_enable" = "1" + + # Enable Processor Thermal Control + register "Device4Enable" = "1" + + # Add PL1 and PL2 values + register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 38, + .tdp_pl4 = 71, + }" + register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 60, + .tdp_pl4 = 105, + }" + #HD Audio register "PchHdaDspEnable" = "1" register "PchHdaAudioLinkHdaEnable" = "0" @@ -149,7 +167,29 @@ #From EDS(575683) device pci 00.0 on end # Host Bridge 0x9A14:U/0x9A12:Y device pci 02.0 on end # Graphics - device pci 04.0 on end # DPTF 0x9A03 + device pci 04.0 on + # Default DPTF Policy for all tglrvp_up3 boards if not overridden + chip drivers/intel/dptf + register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 1000)" + register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 105, SHUTDOWN)" + + # Power Limits Control + register "controls.power_limits.pl1" = "{ + .min_power = 3000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200,}" + register "controls.power_limits.pl2" = "{ + .min_power = 15000, + .max_power = 60000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000,}" + device generic 0 on end + end + end # DPTF 0x9A03 + device pci 05.0 on end # IPU 0x9A19 device pci 06.0 on end # PEG60 0x9A09 device pci 07.0 on end # TBT_PCIe0 0x9A23 diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index 7a5cae1..08c4245 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -109,6 +109,24 @@ # Enable S0ix register "s0ix_enable" = "1"
+ # Enable DPTF + register "dptf_enable" = "1" + + # Enable Processor Thermal Control + register "Device4Enable" = "1" + + # Add PL1 and PL2 values + register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ + .tdp_pl1_override = 9, + .tdp_pl2_override = 35, + .tdp_pl4 = 66, + }" + register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ + .tdp_pl1_override = 9, + .tdp_pl2_override = 40, + .tdp_pl4 = 83, + }" + #HD Audio register "PchHdaDspEnable" = "1" register "PchHdaAudioLinkHdaEnable" = "0" @@ -143,7 +161,29 @@ #From EDS(575683) device pci 00.0 on end # Host Bridge 0x9A14:U/0x9A12:Y device pci 02.0 on end # Graphics - device pci 04.0 on end # DPTF 0x9A03 + device pci 04.0 on + # Default DPTF Policy for all tglrvp_up3 boards if not overridden + chip drivers/intel/dptf + register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 1000)" + register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 105, SHUTDOWN)" + + # Power Limits Control + register "controls.power_limits.pl1" = "{ + .min_power = 3000, + .max_power = 9000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200,}" + register "controls.power_limits.pl2" = "{ + .min_power = 9000, + .max_power = 40000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000,}" + device generic 0 on end + end + end # DPTF 0x9A03 + device pci 05.0 on end # IPU 0x9A19 device pci 06.0 on end # PEG60 0x9A09 device pci 07.0 on end # TBT_PCIe0 0x9A23
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45291
to look at the new patch set (#2).
Change subject: mb/intel/tglrvp: Add DTT support for tglrvp ......................................................................
mb/intel/tglrvp: Add DTT support for tglrvp
Add DTT (Dynamic Tuning Technology) support for Tiger Lake based rvp board. Set power limits and CPU sensor thresholds for DTT based thermal control.
BRANCH=None BUG=Noe TEST=Build and boot on tglrvp board
Change-Id: I0dbee370b8dc9e1e3ae6f1a1101047ac6fd76f53 Signed-off-by: Sumeet R Pawnikar sumeet.r.pawnikar@intel.com --- M src/mainboard/intel/tglrvp/Kconfig M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb 3 files changed, 84 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/45291/2
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45291 )
Change subject: mb/intel/tglrvp: Add DTT support for tglrvp ......................................................................
Patch Set 2: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/45291/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45291/2//COMMIT_MSG@13 PS2, Line 13: Noe None
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Tim Wawrzynczak, Aaron Durbin, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45291
to look at the new patch set (#3).
Change subject: mb/intel/tglrvp: Add DTT support for tglrvp ......................................................................
mb/intel/tglrvp: Add DTT support for tglrvp
Add DTT (Dynamic Tuning Technology) support for Tiger Lake based rvp board. Set power limits and CPU sensor thresholds for DTT based thermal control.
BRANCH=None BUG=None TEST=Build and boot on tglrvp board
Change-Id: I0dbee370b8dc9e1e3ae6f1a1101047ac6fd76f53 Signed-off-by: Sumeet R Pawnikar sumeet.r.pawnikar@intel.com --- M src/mainboard/intel/tglrvp/Kconfig M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb 3 files changed, 84 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/45291/3
Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45291 )
Change subject: mb/intel/tglrvp: Add DTT support for tglrvp ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45291/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45291/2//COMMIT_MSG@13 PS2, Line 13: Noe
None
Done
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Tim Wawrzynczak, Aaron Durbin, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45291
to look at the new patch set (#4).
Change subject: mb/intel/tglrvp: Add DTT support for tglrvp ......................................................................
mb/intel/tglrvp: Add DTT support for tglrvp
Add DTT (Dynamic Tuning Technology) support for Tiger Lake based rvp board. Set power limits and CPU sensor thresholds for DTT based thermal control.
BRANCH=None BUG=None TEST=Build and boot on tglrvp board
Change-Id: I0dbee370b8dc9e1e3ae6f1a1101047ac6fd76f53 Signed-off-by: Sumeet R Pawnikar sumeet.r.pawnikar@intel.com --- M src/mainboard/intel/tglrvp/Kconfig M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb 3 files changed, 84 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/45291/4
Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45291 )
Change subject: mb/intel/tglrvp: Add DTT support for tglrvp ......................................................................
Patch Set 4:
Uploaded patch set 3 with just updated comments.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45291 )
Change subject: mb/intel/tglrvp: Add DTT support for tglrvp ......................................................................
Patch Set 4: Code-Review+2
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45291 )
Change subject: mb/intel/tglrvp: Add DTT support for tglrvp ......................................................................
Patch Set 4: Code-Review+1
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45291 )
Change subject: mb/intel/tglrvp: Add DTT support for tglrvp ......................................................................
mb/intel/tglrvp: Add DTT support for tglrvp
Add DTT (Dynamic Tuning Technology) support for Tiger Lake based rvp board. Set power limits and CPU sensor thresholds for DTT based thermal control.
BRANCH=None BUG=None TEST=Build and boot on tglrvp board
Change-Id: I0dbee370b8dc9e1e3ae6f1a1101047ac6fd76f53 Signed-off-by: Sumeet R Pawnikar sumeet.r.pawnikar@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/45291 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org Reviewed-by: Karthik Ramasubramanian kramasub@google.com --- M src/mainboard/intel/tglrvp/Kconfig M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb 3 files changed, 84 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/mainboard/intel/tglrvp/Kconfig b/src/mainboard/intel/tglrvp/Kconfig index ddb8939..26e5966 100644 --- a/src/mainboard/intel/tglrvp/Kconfig +++ b/src/mainboard/intel/tglrvp/Kconfig @@ -7,12 +7,14 @@ select HAVE_ACPI_TABLES select MAINBOARD_HAS_CHROMEOS select DRIVERS_I2C_HID + select DRIVERS_INTEL_DPTF select DRIVERS_I2C_GENERIC select DRIVERS_I2C_MAX98373 select DRIVERS_INTEL_PMC select DRIVERS_USB_ACPI select DRIVERS_SPI_ACPI select SOC_INTEL_TIGERLAKE + select SOC_INTEL_COMMON_BLOCK_DTT select INTEL_LPSS_UART_FOR_CONSOLE select DRIVERS_INTEL_ISH select EC_ACPI diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 84b965e..ad7eabe 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -121,6 +121,24 @@ # Enable S0ix register "s0ix_enable" = "1"
+ # Enable DPTF + register "dptf_enable" = "1" + + # Enable Processor Thermal Control + register "Device4Enable" = "1" + + # Add PL1 and PL2 values + register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 38, + .tdp_pl4 = 71, + }" + register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 60, + .tdp_pl4 = 105, + }" + #HD Audio register "PchHdaDspEnable" = "1" register "PchHdaAudioLinkHdaEnable" = "0" @@ -155,7 +173,29 @@ #From EDS(575683) device pci 00.0 on end # Host Bridge 0x9A14:U/0x9A12:Y device pci 02.0 on end # Graphics - device pci 04.0 on end # DPTF 0x9A03 + device pci 04.0 on + # Default DPTF Policy for all tglrvp_up3 boards if not overridden + chip drivers/intel/dptf + register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 1000)" + register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 105, SHUTDOWN)" + + # Power Limits Control + register "controls.power_limits.pl1" = "{ + .min_power = 3000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200,}" + register "controls.power_limits.pl2" = "{ + .min_power = 15000, + .max_power = 60000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000,}" + device generic 0 on end + end + end # DPTF 0x9A04:U22/0x9A14:U42 + device pci 05.0 on end # IPU 0x9A19 device pci 06.0 on end # PEG60 0x9A09 device pci 07.0 on end # TBT_PCIe0 0x9A23 diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index 417f23f..3e2b342 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -115,6 +115,24 @@ # Enable S0ix register "s0ix_enable" = "1"
+ # Enable DPTF + register "dptf_enable" = "1" + + # Enable Processor Thermal Control + register "Device4Enable" = "1" + + # Add PL1 and PL2 values + register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ + .tdp_pl1_override = 9, + .tdp_pl2_override = 35, + .tdp_pl4 = 66, + }" + register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ + .tdp_pl1_override = 9, + .tdp_pl2_override = 40, + .tdp_pl4 = 83, + }" + #HD Audio register "PchHdaDspEnable" = "1" register "PchHdaAudioLinkHdaEnable" = "0" @@ -149,7 +167,29 @@ #From EDS(575683) device pci 00.0 on end # Host Bridge 0x9A14:U/0x9A12:Y device pci 02.0 on end # Graphics - device pci 04.0 on end # DPTF 0x9A03 + device pci 04.0 on + # Default DPTF Policy for all tglrvp_up4 boards if not overridden + chip drivers/intel/dptf + register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 1000)" + register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 105, SHUTDOWN)" + + # Power Limits Control + register "controls.power_limits.pl1" = "{ + .min_power = 3000, + .max_power = 9000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200,}" + register "controls.power_limits.pl2" = "{ + .min_power = 9000, + .max_power = 40000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000,}" + device generic 0 on end + end + end # DPTF 0x9A02:Y22/0x9A12:Y42 + device pci 05.0 on end # IPU 0x9A19 device pci 06.0 on end # PEG60 0x9A09 device pci 07.0 on end # TBT_PCIe0 0x9A23
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Karthik Ramasubramanian (Code Review) -
Patrick Georgi (Code Review)
-
Sumeet R Pawnikar (Code Review)
-
Tim Wawrzynczak (Code Review)